Planarization for the integration of CMOS and micromirror arrays

Zheng, Yun; Dutta, Mitra; Kotecki, Carl A.; Zincke, C.

doi:10.1117/12.473435

Cited by 6 publications

(4 citation statements)

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“…And two layers of BCB with spin speed at 5000 rpm and 3000 rpm can further improve the planarization level by reducing the surface topology to about 800 and 600 Å , respectively. The final surface roughness of 600-800 Å is in substantial agreement with the reported value of 600 Å and the measured DOP of 93% and 97% for one and two layers of BCB are also well coinciding with the reported values of 90% and 97% [4,10].…”

Section: Resultssupporting

confidence: 90%

Planarization of CMOS ROIC dies for uncooled detectors

Wang

Chen

et al. 2006

Infrared Physics & Technology

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Section: Resultssupporting

confidence: 90%

Planarization of CMOS ROIC dies for uncooled detectors

Wang

Chen

et al. 2006

Infrared Physics & Technology

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“…With curing temperature 160 ºC the planarization level can be further improved by reducing the surface topology to about 110nm. The final surface roughness (Figure 3) of 83nm with curing temperature 170 ºC is in substantial agreement with the reported value of 800 Å and 600Å and the measured DOP of 95.9% and 97% which planarization was two layers of BCB [5,6]. Figure 2 shows when the softcuring temperature is higher than 170 o C, etching time is 65s, the contacthole can't be etched completely before photoresist floating, so it needs an ICP process to etch polymer films completely.…”

Section: Roughness Of Polymer Films As Planarization Layerssupporting

confidence: 91%

Polymer films as planarization and sacrificial layers for uncooled infrared focal plane arrays

Liu

Cai

et al. 2010

Seventh International Conference on Thin Film Physics and Applications

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This paper presents a planarization procedure using polymer films to achieve a flat CMOS surface of Readout Integrated Circuit (ROIC) for the integration between uncooled infrared focal plane arrays and ROIC. At the same time, the polymer film is also used as the sacrificial layers. After amorphous Silicon (a-Si) film was deposited using plasma enhanced chemical vapor deposition (PECVD), and patterned using inductively coupled plasma (ICP), the polymer sacrificial layer should be removed to form a-Si self-supporting micro-bridge structure. So the thickness of polymer film determine the height of the micro-bridge; the soft curing temperature determines if the contact hole can be etched by developer during the first photolithography; and the rate of dry etching determines whether the sacrificial layers of the structure can be released successfully. In this paper, the curing temperature, surface roughness, etching process of polymer films are systematically researched. On this basis, polymer film as planarization successfully reduces the 2μm height of the bumps on ROIC to less than 83 nm, over the planarized polymer mesas, bolometer arrays are fabricated. Then the polymer film as sacrificial are removed by ICP and 160×120 self-supporting micro-bridge structure arrays are successfully fabricated

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“…One strategy for planarizing a CMOS chip or wafer is the spinning of benzocyclobutene (BCB) with a low hard cure temperature of 200-250 • C. A multilayer structure of SiO 2 /BCB/SiO 2 produced a planarization error of 5% but left an edge bead that required subsequent removal [19]. Another BCB application reduced the surface topography from 2.8 µm to about 60 nm [20]. Recently, chemical mechanical polishing (CMP) has played a key role in allowing continued improvements in integrated circuit density, especially metal interconnection technology [21].…”

Section: Introductionmentioning

confidence: 99%

CMOS chip planarization by chemical mechanical polishing for a vertically stacked metal MEMS integration

Lee

Miller

Bifano

2003

J. Micromech. Microeng.

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In this paper we present the planarization process of a CMOS chip for the integration of a microelectromechanical systems (MEMS) metal mirror array. The CMOS chip, which comes from a commercial foundry, has a bumpy passivation layer due to an underlying aluminum interconnect pattern (1.8 µm high), which is used for addressing individual micromirror array elements. To overcome the tendency for tilt error in the CMOS chip planarization, the approach is to sputter a thick layer of silicon nitride at low temperature and to surround the CMOS chip with dummy silicon pieces that define a polishing plane. The dummy pieces are first lapped down to the height of the CMOS chip, and then all pieces are polished. This process produced a chip surface with a root-mean-square flatness error of less than 100 nm, including tilt and curvature errors.

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Planarization for the integration of CMOS and micromirror arrays

Cited by 6 publications

References 0 publications

Planarization of CMOS ROIC dies for uncooled detectors

Planarization of CMOS ROIC dies for uncooled detectors

Polymer films as planarization and sacrificial layers for uncooled infrared focal plane arrays

CMOS chip planarization by chemical mechanical polishing for a vertically stacked metal MEMS integration

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