Placement of Circuit Modules Using a Graph Space Approach

Fukunaga, Koichi; Stone, Harold S.; Kasai, Tamotsu

doi:10.1109/dac.1983.1585694

“…The first approach is based on assignment, either in one step (to the entire 2-dimensional array of slots) or in two steps (to rows, and then to slots within rows) [9]. The second and more widely-used approach is partitioning: the global placement result is used to derive a horizontal or vertical cut in the layout, and the continuous squared-wirelength optimization is recursively applied to the resulting subproblems (see [6,12,13,16]).…”

Section: Essential Structure Of a Quadratic Placermentioning

confidence: 99%

“…As instance sizes grow larger, movebased (e.g., annealing) methods may be too slow except for detailed placement improvement. Due to its speed and "global" perspective, the so-called quadratic placement technique has received a great deal of attention throughout its development by such authors as Wipfler et al [16], Fukunaga et al [9], Cheng and Kuh [6], Tsay and Kuh [15] and others. Indeed, quadratic placement is reputedly an approach that has been used within commercial tools for placement of standard-cell and gate-array designs.…”

Section: Introductionmentioning

confidence: 99%

Quadratic Placement Revisited

Alpert¹,

Chan²,

Huang³

et al.

Proceedings of the 34th Design Automation Conference

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The "quadratic placement" methodology is rooted in [6] [14] [16] and is reputedly used in many commercial and in-house tools for placement of standard-cell and gate-array designs. The methodology iterates between two basic steps: solving sparse systems of linear equations, and repartitioning. This work dissects the implementation and motivations for quadratic placement. We first show that (i) Krylov subspace engines for solving sparse systems of linear equations are more effective than the traditional successive over-relaxation (SOR) engine [15] and (ii) order convergence criteria can maintain solution quality while using substantially fewer solver iterations. We then discuss the motivations and relevance of the quadratic placement approach, in the context of past and future algorithmic technology, performance requirements, and design methodology. We provide evidence that the use of numerical linear systems solvers with quadratic wirelength objective may be due to the pre-1990's weakness of min-cut partitioners, i.e., numerical engines were needed to provide helpful hints to min-cut partitioners. Finally, we note emerging methodology drivers in deep-submicron design that may require new placement approaches to the placement problem.

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“…The first approach is based on assignment, either in one step (to the entire 2-dimensional array of slots) or in two steps (to rows, and then to slots within rows) [9]. The second and more widely-used approach is partitioning: the global placement result is used to derive a horizontal or vertical cut in the layout, and the continuous squared-wirelength optimization is recursively applied to the resulting subproblems (see [6,12,13,16]).…”

Section: Essential Structure Of a Quadratic Placermentioning

confidence: 99%

“…As instance sizes grow larger, movebased (e.g., annealing) methods may be too slow except for detailed placement improvement. Due to its speed and "global" perspective, the so-called quadratic placement technique has received a great deal of attention throughout its development by such authors as Wipfler et al [16], Fukunaga et al [9], Cheng and Kuh [6], Tsay and Kuh [15] and others. Indeed, quadratic placement is reputedly an approach that has been used within commercial tools for placement of standard-cell and gate-array designs.…”

Section: Introductionmentioning

confidence: 99%

Quadratic placement revisited

Alpert¹,

Chan

²

,

Huang³

et al. 1997

Proceedings of the 34th Annual Conference on Design Automation Conference - DAC '97

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The "quadratic placement" methodology is rooted in [6] [14] [16] and is reputedly used in many commercial and in-house tools for placement of standard-cell and gate-array designs. The methodology iterates between two basic steps: solving sparse systems of linear equations, and repartitioning. This work dissects the implementation and motivations for quadratic placement. We first show that (i) Krylov subspace engines for solving sparse systems of linear equations are more effective than the traditional successive over-relaxation (SOR) engine [15] and (ii) order convergence criteria can maintain solution quality while using substantially fewer solver iterations. We then discuss the motivations and relevance of the quadratic placement approach, in the context of past and future algorithmic technology, performance requirements, and design methodology. We provide evidence that the use of numerical linear systems solvers with quadratic wirelength objective may be due to the pre-1990's weakness of min-cut partitioners, i.e., numerical engines were needed to provide helpful hints to min-cut partitioners. Finally, we note emerging methodology drivers in deep-submicron design that may require new placement approaches to the placement problem.

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“…For a detailed description of the quadratic objec tive function for placement, the reader is referred to [1], [3], or [7]. Briefly stated, the quantity to be mini mized is the sum of the squares of the distances be tween connected devices Γ = | ί Ξ Q [ ( * , -* ; ) 2 + ( y , -y ,…”

Section: Introductionmentioning

confidence: 99%

Near-optimal quadratic-based placement for a class of IC layout problems

Blanks¹

1985

IEEE Circuits Devices Mag.

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Near-optimal placement has long been a coveted goal of IC layout al gorithms. Progress has been hindered because theoretical bounds on place ment quality were unavailable. Such bounds may be obtained for the quadratic metric proposed here. In order to compare traditional placement techniques to these bounds, fast pairwise-interchange techniques were ap plied to placements of homogeneous interchangeable devices on square grids for problem sizes of 100 to 1600 devices. A theoretical model was de veloped that quantitatively explains the deviation from optimal placement quality. Both the experimental and theoretical results surprisingly indi cate an asymptotic approach to optimality with large problem sizes.

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Placement of Circuit Modules Using a Graph Space Approach

Cited by 11 publications

References 5 publications

Quadratic Placement Revisited

Quadratic Placement Revisited

Quadratic placement revisited

Near-optimal quadratic-based placement for a class of IC layout problems

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