Quadratic placement revisited

Abstract

The "quadratic placement" methodology is rooted in [6] [14] [16] and is reputedly used in many commercial and in-house tools for placement of standard-cell and gate-array designs. The methodology iterates between two basic steps: solving sparse systems of linear equations, and repartitioning. This work dissects the implementation and motivations for quadratic placement. We first show that (i) Krylov subspace engines for solving sparse systems of linear equations are more effective than the traditional successive over-relaxation (SOR) engine [15] and (ii) order convergence criteria can maintain solution quality while using substantially fewer solver iterations. We then discuss the motivations and relevance of the quadratic placement approach, in the context of past and future algorithmic technology, performance requirements, and design methodology. We provide evidence that the use of numerical linear systems solvers with quadratic wirelength objective may be due to the pre-1990's weakness of min-cut partitioners, i.e., numerical engines were needed to provide helpful hints to min-cut partitioners. Finally, we note emerging methodology drivers in deep-submicron design that may require new placement approaches to the placement problem.

Hierarchical whitespace allocation in top-down placement

“…w 0 w and w 1 w: (2) For practical purposes, = 1 and may be overly restrictive, as it entails partitioning with zero tolerance in the proportion of site area, while 4 We will sometimes refer to W as whitespace.…”

“…Let R be the number of rows; the expected number n of recursively applied parallel block splits will be n = dlog 2 Re, assuming that rows are distributed evenly between child blocks at every block split.…”

“…Academic and commercial standard-cell placers often apply a top-down, divide-and-conquer approach to define an initial global placement. The top-down approach [20], [13], [2] decomposes the given placement problem into smaller problems by subdividing the placement region, assigning cells to subregions, reformulating constraints, and cutting the netlist-such that good solutions to subproblems combine into good solutions of the original problem. The concept of placement blocks is pivotal.…”

“…In leading-edge microprocessors, the proportion of deliberately introduced free sites, i.e., whitespace, is limited. 2 In other designs, whitespace may be distributed unevenly, and thus some regions may be quite dense. To avoid overcapacity blocks in such regions, total cell area assigned to a block must closely match the area available for cells.…”

“…On the other hand, attempting to 1 See [1] for a review of netlist partitioning formulations and constraints. 2 Deliberate introduction of whitespace may be related to pin-limited designs, limits of power distribution/dissipation density, and the need to maintain autoroutability. While these phenomena are increasingly addressed by packaging and process technology, better architecture and circuit design techniques, multilayer interconnect processes, and cell library design, block-limited designs are becoming increasingly common.…”