Placement-driven technology mapping for LUT-based FPGAs

Abstract

In this paper, we study the problem of placement-driven technology mapping for and EdgeMap consider interconnect delays during mapping, but do not take into consideration the effects of their mapping solution on the final placement. Our work focuses on the interaction between the mapping and placement stages. First, the interconnect delay information is estimated from the placement, and used during the labeling process. A placement-based mapping solution which considers both global cell congestion and local cell congestion is then developed. Finally, a legalization step and detailed placement is performed to realize the design. We have implemented our algorithm in a LUT based FPGA technology mapping package named PDM (Placement-Driven Mapping) and tested the implementation on a set of MCNC benchmarks. We use the tool VPR[1][2] for placement and routing of the mapped netlist. Experimental results show the longest path delay on a set of large MCNC benchmarks decreased by 12.3% on the average.

Simultaneous Technology Mapping and Placement for Delay Minimization

“…1(a), the optimal location of v 3 , which results in the minimum delay, is (3,3). It yields the delay of 14 (10, a v 3 (3, 3), i.e., delay of the subtree rooted at v 3 , + 2 2 , wire-delay from (3,3) to (5,3)). Note that, a v 3 (3, 3) = 10 is from the placement-delay table for v 3 , shown in Fig.…”

“…However, the assumption about the placement of the cells in a tree in a single row is not practical, since the cells are allowed to be placed in different rows in 2-D area. To overcome this limitation, the subsequent work employed iterative technology decomposition, mapping, and placement [5]- [7] to place the primitive gates in a given area, perform mapping with assumptions about the placement of a mapped cell, and then place the mapped netlist or derive the placement of the subject graph from the same for the next iteration.…”

“…end for 9: end for 10: end for wire-delays, the approaches in the paper such as [3], [5], and [6] either assume that the match is placed at some location or iterate between the mapping, placement, and technology decomposition steps. Obviously, these approaches do not claim delay-optimality considering the wire-delays based on the actual placement, even for trees.…”

Incremental physical resynthesis for timing optimization

“…A number of studies on FPGA timing optimization via physical synthesis have been published recently [12,16,17,18], concerning both sequential and combinational logic optimizations.…”

“…With the help of a modified packing routine that strategically leaves logic resources for future logic duplication, creation of new logic via duplication would not disrupt the placement. In [12], simultaneous technology mapping and placement is proposed. Given an initial k-LUT mapping and placement, the netlist is decomposed in-site using gate decomposition, then re-mapped for delay minimization, using layout based delay calculation as guide.…”