Place and Route for Secure Standard Cell Design

Abstract

Side channel attacks can be effectively addressed at the circuit level by using dynamic differential logic styles. A key problem is to guarantee a balanced capacitive load at the differential outputs of the logic gates. The main contribution to this load is the capacitance associated with the routing between cells. This paper describes a novel design methodology to route a design in which multiple differential pairs are present. The methodology is able to route 20K+ differential routes. The differential routes are always routed in adjacent tracks and the parasitic effects between the two wires of each differential pair are balanced. The methodology is developed on top of a commercially available EDA tool. It has been developed as part of a secure digital design flow to protect security applications against Differential Power Analysis attacks. Experimental results indicate that a perfect protection is attainable with the aid of the proposed differential routing strategy.

Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style

“…As the main factors of the DPA leakage in WDDL, the following two contents have been pointed out [7,8] We here describe the factor of the above-mentioned leakage in detail. At first, we explain the main factor of leakage in F1.…”

“…Therefore, incidental leakage can be likely to improve with the place-and-route in the manual operation or the semi-automatic operation using the special constraints. Actually, Tiri et al and Guilley et al proposed "Fat Wire" [7] and "Backend Duplication" [11], respectively as a countermeasure in the place-and-route to improve the DPA-resistance.…”

“…However, RSL requires the special CMOS gates to perform effective implementing process and the special constraints of timing to assure the security. Wave Dynamic Differential Logic (WDDL) [6], which applies the dual-rail synchronous circuit, must adopt the specialized place-and-route method to adjust the loading capacitance for implementing of the secure circuit [7]. In addition, Suzuki et al present the fact that DPA leakage occurs when there are differences in the delay time between the input signals at the WDDL gates [5,8].…”

Divided Backend Duplication Methodology for Balanced Dual Rail Routing

“…However, in practice it is difficult to have logic without inversion. This is Fat Wire was proposed by Tiri and Verbauwhede [1] to address routing imbalances in DRP logic styles. In this methodology a Fat Wire is constructed by two adjacent normal wires.…”

“…To address the routing problem, to date the following proposals have been put forward: DWDDL [3], FatWire [1], Backend Duplication [2], Three Phase Dual Rail [13], Path Switching [9], Double WDDL [14] and an iterative correction flow [15]. Of these, three proposals [1,2,3] impose some constraints on backend implementation flows. Three Phase Dual Rail [13] tries to avoid the routing problem by introducing a third phase, which is an additional overhead.…”