Pixel/DRAM/logic 3-layer stacked CMOS image sensor technology

Tsugawa, Hidenobu; Takahashi, Hiroshi; Nakamura, Ryoichi; Umebayashi, Taku; Ogita, Tomoharu; Okano, Hitoshi; Iwase, Kazuya; Kawashima, Hiroshi; Yamasaki, Takahiro; Yoneyama, D.; Hashizume, Jiro; Nakajima, Tasuku; Murata, Kenji; Kanaishi, Y.; Ikeda, Kazuhiro; Tatani, Keiji; Nagano, Takashi; Nakayama, Hiroki; Tsutomu, Haruta; Nomoto, Takuya

doi:10.1109/iedm.2017.8268317

Cited by 35 publications

(11 citation statements)

References 4 publications

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“…(1) Considerable reduction in white spot defects by using a C 3 H 6 -ion-implanted double epitaxial Si wafer was demonstrated in the fabrication of CMOS image devices. (2) The reduction in white spot defects of the C 3 H 6 -ion-implanted double epitaxial Si wafer occurred owing to the high gettering capability for metallic impurities introduced during the device fabrication process and the suppression of O diffusion into the device active layer. The higher gettering capability of the C 3 H 6 -ion-implanted double epitaxial Si wafer was also effective for metallic impurities introduced during device fabrication.…”

Section: Discussionmentioning

confidence: 99%

“…There is a high demand for the fabrication of high-performance CMOS image sensors with characteristics such as high sensitivity, high resolution, and high-speed image data processing owing to the expansion of the CMOS image sensor market. Recently, three-dimensional (3D)-stacked backside illuminated (BSI) CMOS image sensors allowing multiple functions of image sensors have attracted attention [ 1 , 2 , 3 ]. The fabrication of 3D-stacked CMOS image sensors is achieved by 3D integration technology that enables the stacking of different kinds of circuit blocks, such as sensor, memory, and logic blocks, into one chip with mainly Cu through-silicon via (TSV) technology.…”

Section: Introductionmentioning

confidence: 99%

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Reduction of Dark Current in CMOS Image Sensor Pixels Using Hydrocarbon-Molecular-Ion-Implanted Double Epitaxial Si Wafers

Onaka‐Masada

Kadono

Okuyama

et al. 2020

Sensors

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The impact of hydrocarbon-molecular (C3H6)-ion implantation in an epitaxial layer, which has low oxygen concentration, on the dark characteristics of complementary metal-oxide-semiconductor (CMOS) image sensor pixels was investigated by dark current spectroscopy. It was demonstrated that white spot defects of CMOS image sensor pixels when using a double epitaxial silicon wafer with C3H6-ion implanted in the first epitaxial layer were 40% lower than that when using an epitaxial silicon wafer with C3H6-ion implanted in the Czochralski-grown silicon substrate. This considerable reduction in white spot defects on the C3H6-ion-implanted double epitaxial silicon wafer may be due to the high gettering capability for metallic contamination during the device fabrication process and the suppression effects of oxygen diffusion into the device active layer. In addition, the defects with low internal oxygen concentration were observed in the C3H6-ion-implanted region of the double epitaxial silicon wafer after the device fabrication process. We found that the formation of defects with low internal oxygen concentration is a phenomenon specific to the C3H6-ion-implanted double epitaxial wafer. This finding suggests that the oxygen concentration in the defects being low is a factor in the high gettering capability for metallic impurities, and those defects are considered to directly contribute to the reduction in white spot defects in CMOS image sensor pixels.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Reduction of Dark Current in CMOS Image Sensor Pixels Using Hydrocarbon-Molecular-Ion-Implanted Double Epitaxial Si Wafers

Onaka‐Masada

Kadono

Okuyama

et al. 2020

Sensors

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“…In fact, as it will be explained in paragraph 3, crosstalk strongly depends on the silicon layer thickness. Papers in recent literature report that for pixel sizes of 1 µm to 3 µm, the silicon thickness is about 3-4 µm [19]- [25]. Following this analysis, we discuss simulation of crosstalk when considering a pixel size of 3 µm, a silicon thickness of 4 µm, a pn junction width and depth of 1.5 µm and a distance between two adjacent pn junctions of 1 µm.…”

Section: B Back-side Illuminationmentioning

confidence: 97%

Simulation of CMOS APS Operation and Crosstalk in SPICE With Generalized Devices

Rossi

Sallèse

2020

IEEE J. Electron Devices Soc.

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We present SPICE simulations of a CMOS APS pixel element consisting of the optical sensor with the sensing circuit. The photodiode is simulated at the physics level by means of the socalled Generalized Devices, without any predefined compact model. Conversely, regular compact models are used for MOSFETs present in the circuit. Modeling with Generalized Devices takes into account in SPICE simulations both the layout and the physics of the photodiode, i.e., drift-diffusion transport, optical generation and recombination of excess carriers, capacitive effects and surface recombination. Moreover, electrical coupling between two adjacent pixels, i.e., the electrical crosstalk, is well predicted by the network of Generalized Devices. This approach is supported by TCAD Sentaurus simulations and opens the way to full SPICE simulation of Active Pixel Sensor from the circuit down to the semiconductor level within the same circuit simulation tool.

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“…Fig. 8 Chip-to-chip bonding and interconnect methods with (a) direct dielectric bonding followed by via-last TSVs for chipto-chip interconnect, (b) hybrid bonding at peripheral area, and (c) hybrid bonding under pixel arrays 1.22 lm Â 1.22 lm pixel and total of 19.3 MP is demonstrated with this 7.73 mm (diagonal) three-chip stacked BSI-CIS [6,7]. The cross section of the stacked chips is shown in Fig.…”

Section: Rgb -Near Infrared Backside Illuminated-cmosmentioning

confidence: 99%

“…The proposed 3D integration has been altered by newly implemented enabling technologies and feature size reduction. A few major breakthroughs such as backside illuminated (BSI) CIS in 2009, chip stacking in 2012, and pixel-DRAM-logic three-chip stacking in 2015 [7], and Cu-Cu hybrid bonding in 2016 [6,22,67] lead to the current state-of-the-art technology platforms.…”

Section: Introductionmentioning

confidence: 99%

Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

Lu¹

2021

Journal of Electronic Packaging

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Numerous technology breakthroughs have been made in image sensor development in the past two decades. Image sensors have evolved into a technology platform to support many applications. Their successful implementation in mobile devices has accelerated market demand and established a business platform to propel continuous innovation and performance improvement extending to surveillance, medical, and automotive industries. This overview briefs the general camera module and the crucial technology elements of chip stacking architectures and advanced interconnect technologies. This study will also examine the role of pixel electronics in determining the chip stacking architecture and interconnect technology of choice. It is conducted by examining a few examples of CMOS Image Sensors (CIS) for different functions such as visible light detection, Single Photon Avalanche Photodiode (SPAD) for low light detection, rolling shutter and global shutter, and depth sensing and Light Detection And Ranging (LiDAR). Performance attributes of different architectures of chip stacking are overviewed. Direct bonding followed by Via-last through silicon via (Via-last TSV) and hybrid bonding (HB) technologies are identified as newer and favorable chip-to-chip interconnect technologies for image sensor chip stacking. The state-of-the-art ultra-high-density interconnect manufacturability is also highlighted.

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Pixel/DRAM/logic 3-layer stacked CMOS image sensor technology

Cited by 35 publications

References 4 publications

Reduction of Dark Current in CMOS Image Sensor Pixels Using Hydrocarbon-Molecular-Ion-Implanted Double Epitaxial Si Wafers

Reduction of Dark Current in CMOS Image Sensor Pixels Using Hydrocarbon-Molecular-Ion-Implanted Double Epitaxial Si Wafers

Simulation of CMOS APS Operation and Crosstalk in SPICE With Generalized Devices

Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

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