PipeRench: A virtualized programmable datapath in 0.18 micron technology

Schmit, Herman; Whelihan, David; Tsai, A.; Moe, Matthew; Levine, B.; Taylor, Renée R.

doi:10.1109/cicc.2002.1012767

Cited by 102 publications

(47 citation statements)

References 3 publications

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“…The programmable connections in the data-path interconnect in our fabric are modeled as multiplexers somewhat similar to those in RaPiD. Unlike RAP [5] whose ALUs are arranged in a chess board style, the fabric model used in our research has a striped configuration like that of PipeRench [15] but without register files.…”

Section: Acceleration With Custom Hardwarementioning

confidence: 99%

Interconnect Customization for a Coarse-grained Reconfigurable Fabric

Mehta

Slander

Baz

et al. 2007

2007 IEEE International Parallel and Distributed Processing Symposium

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This paper describes several system-level interconnection strategies for a coarse-grained reconfigurable fabric designed for low-energy hardware acceleration. A small, representative sub-graph for signal and image processing applications is used to predict the success of mapping larger applications onto the fabric device with these different interconnection strategies, which include 32:1, 8:1, 5:1, 4:1, 3553:1 (3:1, 5:1, 5:1, 3:1) and 355:1 (3:1, 5:1, 5:1) cardinalities. Three mapping techniques are presented and used to complete mappings onto several of these fabric instances including a mixed integer linear programming technique, a constraint programming approach, and a greedy heuristic. We present results for area (in number of required rows), power, delay, and energy as well as run times for mapping a set of signal and image processing benchmarks onto each of these interconnects. Our results indicate that the 5:1 interconnect provides the best overall results and does not require any additional hardware resources than the baseline 4:1 technique. When compared with other implementation strategies, the reconfigurable fabric energy consumption, using 5:1-based interconnect, is within 5-10X of a direct ASIC implementation, is 10X better than an Virtex II Pro FPGA and is 100X better than an Intel XScale processor.

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Section: Acceleration With Custom Hardwarementioning

confidence: 99%

Interconnect Customization for a Coarse-grained Reconfigurable Fabric

Mehta

Slander

Baz

et al. 2007

2007 IEEE International Parallel and Distributed Processing Symposium

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“…Currently, only hundreds of processor blocks can be integrated on a single device unlike the tens of thousands of logic blocks found on current FPGAs but with increased integration this will expand quickly. These coarse-grained architectures also appear to be moving away from heterogeneity as many of the recent designs are largely homogeneous [47,175,192,206].…”

Section: Coarse-grained Fpgasmentioning

confidence: 99%

“…The original developments in this area favored logic blocks with relatively simple functional unit blocks. This included, PipeRench, an architecture based on 8-bit 3-LUT logic blocks with additional circuitry to improve arithmetic operations [86,175], CHESS, which was based on a 4-bit ALU [145], RaPiD, which contained a mixture of 16-bit ALUs, multipliers and memories [77] and DAPDNA-2, which combined 32-bit ALUs, delay elements, memories, and external memory access units [173].…”

Section: Coarse-grained Fpgasmentioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

317

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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“…However, reconfiguration is not instantaneous and requires suspension of normal execution. PipeRench [20] improves on this using a time-multiplexing technique, reused by MCGREP, but the PipeRench array is not tightly integrated into the CPU. ReRisc [24] tightly integrates a RISC core and a CGRA with configuration cache, permitting fast reconfiguration in the case of a cache hit.…”

Section: Related Workmentioning

confidence: 99%

“…In contrast, CGRAs have lower reconfiguration costs than FGRAs [24], due to the reduced size of the required configuration bitstream, which is helpful in an RTS that must remain responsive. Some CGRAs, such as PipeRench [20], introduce a pipeline that allows the CGRA configuration to be changed every clock cycle.…”

Section: Design Principlesmentioning

confidence: 99%