Pipelined extended‐counting for 3D‐stacked CMOS image sensors

Abstract

A novel multi-stage pipelined extended-counting (EC) IDS for 3D-stacked CMOS image sensors is presented, which combines the benefits of a pipelined ADC, a first-order IDS ADC and the EC principle in order to simultaneously achieve a high resolution and a high frame rate for 3D-stacked imagers. By assigning each stage of the pipeline to a sub-column of pixels while choosing another input stage of the pipeline when a sub-column has been read out, discontinuous rolling shutter artefacts like chopped images can be eliminated and frame rates up to 340 fps can be achieved for imagers with 8 K resolution.

Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

“…5) Pixel Sub-Column Readout With Sub-Column Configurable Pipeline ADC: In this readout architecture [4], [16], each pixel sub-column SC pixel (i, j ) is assigned to a column ADC (see Fig. 11(a)).…”

“…Another ADC that is becoming popular in CIS is the incremental (I) [16], [35]- [42]. The amount of cycles is dependent on the order (N order ) and resolution of the quantizer (N Q ).…”

“…However, a higher-order I ADC results in a more complex system and an increased area, which is disadvantageous for 3D-stacked CIS. As a result, I ADCs reported in literature are mostly implemented as second-order I with N B,Q = 1 [35], [40]- [42], first-order I with multi-bit quantizer [36], [37] or extended-counting (EC) I [16], [38], [39]. The operation of the latter architecture resembles a two-step converter and its operation is based on the fact that the residue is available at the output of the last integrator in the loop, which is further refined by a fine ADC [43].…”

Design Improvements on Fast, High-Order, Incremental Sigma-Delta ADCs for Low-Noise Stacked CMOS Image Sensors

“…However, in 3D-stacked integrated sensors, the RS addressing becomes critical due to spreading the amount of total pixels over the sub-regions, consequently worsening the usual RS image distortion, as it may create false discontinuities [11,12] of the objects from the Filed-of-View (FoV) from adjacent sub-regions, which in turn would be visible in the resulting images. However, in 3D-stacked integrated sensors, the RS addressing becomes critical due to spreading the amount of total pixels over the sub-regions, consequently worsening the usual RS image distortion, as it may create false discontinuities [11,12] of the objects from the Filed-of-View (FoV) from adjacent sub-regions, which in turn would be visible in the resulting images.…”

“…Depending on the circuits' arrangement, discontinuities may occur depending on the shutter direction implemented in the stacked sensor for each region of pixels belonging to a particular readout circuitry [12]. Given these issues, the use of RS pixels in 3D-stacked sensors disturbs and distorts the images much more than in 2D flat sensors, if classically operated.…”