PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning

Song, Linghao; Qian, Xuehai; Li, Hai; Chen, Yiran

doi:10.1109/hpca.2017.55

Cited by 645 publications

(400 citation statements)

References 49 publications

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“…[118] Furthermore, it removes the high-cost ADC/DAC components and replaces with spiking-based read/output circuits. [118] Furthermore, it removes the high-cost ADC/DAC components and replaces with spiking-based read/output circuits.…”

Section: Rram-based In-memory Computing Microarchitecturementioning

confidence: 99%

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Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

Yan

Qiao

et al. 2019

Advanced Intelligent Systems

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In‐memory computing is a computing scheme that integrates data storage and arithmetic computation functions. Resistive random access memory (RRAM) arrays with innovative peripheral circuitry provide the capability of performing vector‐matrix multiplication beyond the basic Boolean logic. With such a memory–computation duality, RRAM‐based in‐memory computing enables an efficient hardware solution for matrix‐multiplication‐dependent neural networks and related applications. Herein, the recent development of RRAM nanoscale devices and the parallel progress on circuit and microarchitecture layers are discussed. Well suited for analog synapse and neuron implementation, RRAM device properties and characteristics are emphasized herein. 3D‐stackable RRAM and on‐chip training are introduced in large‐scale integration. The circuit design and system organization of RRAM‐based in‐memory computing are essential to breaking the von Neumann bottleneck. These outcomes illuminate the way for the large‐scale implementation of ultra‐low‐power and dense neural network accelerators.

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Section: Rram-based In-memory Computing Microarchitecturementioning

confidence: 99%

“…Shafiee et al [116] Microarchitecture DAC/ADC Processor/macro DNN, CNN ImageNet [139] Song et al [118] Microarchitecture IFC Processor DNN, CNN Image recognition, NN c) training…”

Section: Workmentioning

confidence: 99%

Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

Yan

Qiao

et al. 2019

Advanced Intelligent Systems

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“…By leveraging the ReRAM structure, various CNN accelerators have been proposed for the inference or training [5,8]. The kernel in a convolution layer is a tensor with 4 dimensions and its mapping on crossbar requires a complicated design [8,9]. Fig.…”

Section: A Reram-based Cnn Acceleratormentioning

confidence: 99%

“…Once a round of computation in sub-crossbars is completed, we add the output from corresponding SCs to obtain the final deconvolution results. Thanks to the vertical sum-up design in the existing ReRAM-based accelerators [8,12], no extra circuitry is needed to realize the addition operations in pixelwise mapping.…”

Section: B Red Architecturementioning

confidence: 99%

“…Resistive RAM (ReRAM) has been taken as a competitive technology for PIM implementation due to its low-energy and high-efficient vector-matrix multiplications performed on the crossbar structure. Various ReRAM-based accelerators [5][6][7][8][9][10] have been presented for fast and efficient convolution, showing great advantages of ReRAM over the CMOS-based counterparts.…”

Section: Introductionmentioning

confidence: 99%

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RED: A ReRAM-based Deconvolution Accelerator

Fan¹,

Li²,

Li³

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Deconvolution has been widespread in neural networks. For example, it is essential for performing unsupervised learning in generative adversarial networks or constructing fully convolutional networks for semantic segmentation. Resistive RAM (ReRAM)-based processing-in-memory architecture has been widely explored in accelerating convolutional computation and demonstrates good performance. Performing deconvolution on existing ReRAM-based accelerator designs, however, suffers from long latency and high energy consumption because deconvolutional computation includes not only convolution but also extra add-on operations. To realize the more efficient execution for deconvolution, we analyze its computation requirement and propose a ReRAM-based accelerator design, namely, RED. More specific, RED integrates two orthogonal methods, the pixel-wise mapping scheme for reducing redundancy caused by zero-inserting operations and the zero-skipping data flow for increasing the computation parallelism and therefore improving performance. Experimental evaluations show that compared to the state-ofthe-art ReRAM-based accelerator, RED can speed up operation 3.69∼31.15× and reduce 8%∼88.36% energy consumption. * These three authors contributed equally to this work.

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Emerging Memory Structures for VLSI Circuits

Garzón¹,

Yavits²,

Lanuzza³

et al. 2022

Wiley Encyclopedia of Electrical and Electronics Engineering

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Ever since the emergence of the electrical computer and the Von Neumann model, computer architects have adhered to a well‐structured hierarchy of memory solutions, clearly trading off performance and capacity with cost. The ubiquitous memory technologies, dominated by SRAM, DRAM, Flash, and magnetic hard disks, are each situated in a well‐defined location within this hierarchy. However, as processes have scaled into deep nanometer feature sizes and the demand for larger capacities and bandwidths increases, these traditional options face tough challenges and may be limited in their ability to continue to provide the new requirements. New technologies, such as phase change memory (PCM), magnetic RAM (MRAM), and resistive RAM (RRAM), have been researched and developed over the recent past in an attempt to meet these demands and replace some or all of the traditional technologies. In this article, the primary technologies are overviewed, including those that currently fill the memory hierarchy pyramid, the primary candidates to join or replace them in the near‐term, and a number of newer candidates that may arise as legitimate solutions in the farther term. In addition, an overview of the current state of processing within the emerging memory technologies is provided, as an attempt to break free of the traditional Von Neumann paradigm to overcome the energy and performance bottlenecks in modern systems.

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PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning

Cited by 645 publications

References 49 publications

Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

RED: A ReRAM-based Deconvolution Accelerator

Emerging Memory Structures for VLSI Circuits

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