Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation

Patil, Harish; Cohn, Robert; Charney, Mark; Kapoor, Rajiv; Sun, Andrew; Karunanidhi, Anand

doi:10.1109/micro.2004.28

Cited by 278 publications

(130 citation statements)

References 15 publications

Supporting

Mentioning

124

Contrasting

Unclassified

Order By: Relevance

“…Using a large interval length will result in a smaller number of phases. In addition, some research groups (e.g., Intel) simulate large samples (on the size of 300 million instructions or more), so that they do not have to deal with warmup issues [23].…”

Section: Initial Simpoint Resultsmentioning

confidence: 99%

Motivation for Variable Length Intervals and Hierarchical Phase Behavior

Lau

Perelman

Hamerly

et al. 2005

IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005.

View full text Add to dashboard Cite

show abstract

Section: Initial Simpoint Resultsmentioning

confidence: 99%

Motivation for Variable Length Intervals and Hierarchical Phase Behavior

Lau

Perelman

Hamerly

et al. 2005

IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005.

View full text Add to dashboard Cite

show abstract

“…The model executes user-mode x86-64 code by cracking instructions into µops (using a modified PTLsim [58] decoder). To collect each checkpoint/trace, we use a custom Pin-tool [34] and use PinPoints [44] One parameter of our model is the sensitivity of design to static power. The parameters in our model are based on a 28nm FDSOI (fully depleted silicon on insulator) process technology as described in [19].…”

Section: Methodsmentioning

confidence: 99%

The heterogeneous block architecture

Fallin¹,

Wilkerson

Mutlu³

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

View full text Add to dashboard Cite

This paper makes two new observations that lead to a new heterogeneous core design. First, we observe that most serial code exhibits fine-grained heterogeneity: at the scale of tens or hundreds of instructions, regions of code fit different microarchitectures better (at the same point or at different points in time). Second, we observe that by grouping contiguous regions of instructions into blocks that are executed atomically, a core can exploit this heterogeneity: atomicity allows each block to be executed independently on its own execution backend that fits its characteristics best.Based on these observations, we propose a fine-grained heterogeneous design that combines heterogeneous execution backends into one core. Our core design, the heterogeneous block architecture (HBA), breaks the program into blocks of code, determines the best backend for each block, and specializes the block for that backend. As an initial, concrete design, we combine out-of-order, VLIW, and in-order backends, using simple heuristics to choose backends. We compare HBA to multiple baseline core designs (including monolithic out-of-order, clustered out-of-order, in-order and a state-of-the-art heterogeneous core design) and show that HBA can provide significantly better energy efficiency than all designs at similar performance. Averaged across 184 traces from a wide variety of workloads, HBA reduces core power by 36.4% and energy per instruction by 31.9% compared to a 4-wide out-of-order core. We conclude that HBA provides a flexible substrate for exploiting fine-grained heterogeneity, enabling new energy-performance tradeoff points in core design.

show abstract

“…After compilation, the compiler unblocks the executor (7) and the executor switches context again to execute the JITted code (8). When the JITted code is done, we again switch back to the executor (9,10), which signals to the compiler (11). The compiler then switches back to the context where the JITted code stopped and resumes with interpreted code (12).…”

Section: A Designmentioning

confidence: 99%

“…For this purpose we use the program instrumentation tool PIN [11]. We modified the "proccount" PIN tool to keep record of invoked functions and the number of instructions executed per function.…”

Section: A Effectivenessmentioning

confidence: 99%

Lobotomy: An Architecture for JIT Spraying Mitigation

Jauernig¹,

Neugschwandtner

Platzer

et al. 2014

2014 Ninth International Conference on Availability, Reliability and Security

View full text Add to dashboard Cite

Abstract-JIT spraying has an assured spot in an attacker's toolkit for Web browser exploitation: With JIT spraying an attacker is able to circumvent even the most sophisticated defense strategies against code injection, including address space layout randomization (ASLR), data execution prevention (DEP) and stack canaries.In this paper, we present LOBOTOMY, an architecture for building injection-safe JIT engines. LOBOTOMY is secure by design: it separates compiler and executor of a JIT engine in different processes that share the memory regions containing the compiled code. This allows us to use least-privilege access rights for both processes, preventing memory regions to be mapped with write-and execute-rights at the same time.Our proof-of-concept implementation that modifies the wellknown Firefox JIT engine Tracemonkey shows both the effectiveness and real-world feasibility of our architecture. Additionally, we provide a thorough evaluation of our version compared to an unmodified baseline and competing approaches.

show abstract

Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation

Abstract: Abstract

Cited by 278 publications

References 15 publications

Motivation for Variable Length Intervals and Hierarchical Phase Behavior

Motivation for Variable Length Intervals and Hierarchical Phase Behavior

The heterogeneous block architecture

Lobotomy: An Architecture for JIT Spraying Mitigation

Contact Info

Product

Resources

About