Pin Accessibility-Driven Detailed Placement Refinement

Ding, Yixiao; Chu, Chris; Mak, Wai-Kei

doi:10.1145/3036669.3036679

Cited by 35 publications

(9 citation statements)

References 14 publications

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“…The site number in the overlapping region is 5, and the site number of net is 10, as shown in Figure 5(b). The probability of being inside the vertical overlapping region # # equals 5 10 . As a result, the probability ( ) in Figure 5(b) equals 5 10 × 2 3 × 1 3 = 1 9 .…”

Section: Pin Access Congestion Estimationmentioning

confidence: 99%

“…One main issue that makes the detailed routing problem di cult is the pin access challenge, as the layouts become denser and the pitch distance becomes ner [5]. A standard cell could have multiple pins, and each pin might have multiple access points for via insertion to build connections with wire segments in some metal layer (say, metal-2 layer).…”

Section: Introductionmentioning

confidence: 99%

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Routability-aware pin access optimization for monolithic 3D designs

Wang

Chang

2020

Proceedings of the 39th International Conference on Computer-Aided Design

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Section: Pin Access Congestion Estimationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Routability-aware pin access optimization for monolithic 3D designs

Wang

Chang

2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…As manufacturing technology nodes are continuously evolved into sub-10nm, the detailed routing has been more challenging [1]. One of the major difficulties in the detailed routing is exposed by the resolution limitations coming from the diffraction limit of optical lithography which has 193nm (i.e., 193i) wavelength [11,12,23]. Although recent multi-patterning techniques [4,18,19] enable to deliver 10nm and sub-10nm technology nodes to foundries, they induce more complex conditional design rules for manufacturability which are new hurdles in the detailed routing procedure [2].…”

Section: Introductionmentioning

confidence: 99%

“…Our proposed SAT formulation adopts representative conditional design rules such as Minimum Area Rule, End-of-Line Spacing Rule, and Via Rule from[10,14,16].Geometric Variable (GV). Logical Expressions(11)(12)(13) represent the feasibility of Geometric Variable (GV) determined by the EOL of a metal segment as shown in…”

mentioning

confidence: 99%

Road

Park

Kang

Kim

et al. 2019

Proceedings of the 2019 International Symposium on Physical Design

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Routability diagnosis has increasingly become the bottleneck in detailed routing for sub-10nm technology due to the limited tracks, high density, and complex design rules. The conventional ways to examine the routability of detailed routing are ILP-and SAT-based techniques. However, once we identify the routability, the diagnosis remains an open problem for physical designers. In this paper, we propose a novel framework, called ROAD, which diagnoses explicit reasons for routing failures. The proposed ROAD framework utilizes a diagnosis-friendly SAT formulation to represent design's layout and diagnoses the routability with SAT solving techniques. Based on the diagnosis, ROAD provides human-interpretable explanations for conflicted routing conditions. To show the practical value of our framework, we also generate comprehensive test-sets that enable exhaustive exploration of layouts based on Rent's rule. We demonstrate that ROAD successfully examines conflict causes for diverse pin layouts. Throughout extensive diagnosis, we also present several key findings for design failure. ROAD performs routability diagnosis within 2 minutes on average for 90 grids testsets, while diagnosing the exact causes of routing failures in terms of congestion and conditional design rules.

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“…The librarylevel optimizations are based on the final power, performance and area metrics from an entire back-end design flow, which also generates valuable baseline results for future research studies. Therefore, we anticipate a much broader academic impact, while leveraging very recent research on SC library evaluation and optimization [14][15][16], automatic SC synthesis [17][18][19], SC-driven placement [20][21][22][23][24] and routing [25][26][27][28] towards a full synthesis research flow [29].…”

Section: Introductionmentioning

confidence: 99%

Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper)

Shah

Evans

et al. 2017

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Standard cell libraries are the foundation for the entire backend design and optimization flow in modern application-specific integrated circuit designs. At 7nm technology node and beyond, standard cell library design and optimization is becoming increasingly di cult due to extremely complex design constraints, as described in the ASAP7 process design kit (PDK). Notable complexities include discrete transistor sizing due to FinFETs, complicated design rules from lithography and restrictive layout space from modern standard cell architectures. The design methodology presented in this paper enables e cient and high-quality standard cell library design and optimization with the ASAP7 PDK. The key techniques include exhaustive transistor sizing for cell timing optimization, transistor placement with generalized Euler paths and back-end design prototyping for library-level explorations.

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Pin Accessibility-Driven Detailed Placement Refinement

Cited by 35 publications

References 14 publications

Routability-aware pin access optimization for monolithic 3D designs

Routability-aware pin access optimization for monolithic 3D designs

Road

Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper)

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