2008
DOI: 10.1109/memsys.2008.4443757
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Piezoresistive effect in top-down fabricated silicon nanowires

Abstract: Encouraged by the results of He and Yang [1], we have designed and fabricated silicon test chips to investigate the piezoresistive properties of both crystalline and polycrystalline nanowires using a top-down approach, in order to comply with conventional fabrication techniques. The test chip consists of 5 silicon nanowires and a reference resistor, each with integrated contacts for electrical 4-point measurements. We show an increase in the piezoresistive effect of 633% compared to bulk silicon. Preliminary t… Show more

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Cited by 50 publications
(43 citation statements)
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“…This suggests an electrostatic origin for the giant PZR, for example due to electromechanically active interface states [11]. Although there is some evidence for such a component in the anomalous PZR at very high stresses [12,13], in most cases PZR close to the bulk value is observed [14][15][16][17][18][19], even in depleted [16] or gated [19] SiNWs. It is important to clarify this situation in part because a novel surface electromechanical phenomenon may be involved, but also in the context of sensing and strain effects on the electronic properties of future nanoscale silicon devices.…”
mentioning
confidence: 99%
“…This suggests an electrostatic origin for the giant PZR, for example due to electromechanically active interface states [11]. Although there is some evidence for such a component in the anomalous PZR at very high stresses [12,13], in most cases PZR close to the bulk value is observed [14][15][16][17][18][19], even in depleted [16] or gated [19] SiNWs. It is important to clarify this situation in part because a novel surface electromechanical phenomenon may be involved, but also in the context of sensing and strain effects on the electronic properties of future nanoscale silicon devices.…”
mentioning
confidence: 99%
“…Such effects can diminish the performance of the nanoelectromechanical amplifier by increasing the operating temperature in the beam and power dissipation and therefore reducing the mechanical quality factor. However, the large piezoresistive coefficient observed in silicon nanowires [17][18][19] , along with the increase in the thermal expansion coefficient [20][21] , is expected to compensate for and even improve the overall device performance.…”
Section: Discussion Scaling and Performance Improvementmentioning
confidence: 99%
“…Nanowire devices fabricated by T. Toriyama et al [7] and He and Yang et al [8] both had a suspended structure. K. Reck et al [9] produced p-type silicon nanowires from 140nm to 480nm wide on solid substrates. They observed an enhancement of 633% in piezoresistance for the smallest nanowire of 140nm width and 200nm thickness under compressive stress.…”
Section: Introductionmentioning
confidence: 99%