Physics-Based SPICE Model of a-InGaZnO Thin-Film Transistor Using Verilog-A

Jeon, Yong Woo; Hur, Inseok; Kim, Yong-Sik; Bae, Myunghan; Jung, Hyun Kwang; Kong, Dongsik; Kim, Woojoon; Kim, Jaehyeong; Jang, Jaeman; Kim, Dong Myong; Kim, Dae Hwan

doi:10.5573/jsts.2011.11.3.153

Cited by 6 publications

(2 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Reflecting the repeated stress/recovery in AC bias, a real-time ∆V T was successfully applied in the inverter simulation. In detail, each function presented in Table 1 was entered into the V T parameters in the analytical I-V model of Verilog-A [30]. After configuring an IGZO NMOS-only inverter in HSPICE, the SEF model and the extracted parameters were used for both device simulation and transient AC simulation.…”

Section: δV T [V]mentioning

confidence: 99%

Reliability-Aware SPICE Compatible Compact Modeling of IGZO Inverters on a Flexible Substrate

et al. 2021

View full text Add to dashboard Cite

Accurate circuit simulation reflecting physical and electrical stress is of importance in indium gallium zinc oxide (IGZO)-based flexible electronics. In particular, appropriate modeling of threshold voltage (VT) changes in different bias and bending conditions is required for reliability-aware simulation in both device and circuit levels. Here, we present SPICE compatible compact modeling of IGZO transistors and inverters having an atomic layer deposition (ALD) Al2O3 gate insulator on a polyethylene terephthalate (PET) substrate. Specifically, the modeling was performed to predict the behavior of the circuit using stretched exponential function (SEF) in a bending radius of 10 mm and operating voltages ranging between 4 and 8 V. The simulation results of the IGZO circuits matched well with the measured values in various operating conditions. It is expected that the proposed method can be applied to process improvement or circuit design by predicting the direct current (DC) and alternating current (AC) responses of flexible IGZO circuits.

show abstract

Section: δV T [V]mentioning

confidence: 99%

Reliability-Aware SPICE Compatible Compact Modeling of IGZO Inverters on a Flexible Substrate

et al. 2021

View full text Add to dashboard Cite

show abstract

“…Various Verilog-A models have been developed for a-IGZO TFTs, 15,16 for example, Shabanpour et al 17 adapted the technology-dependent, RPI a-Si Verilog-A model for a-IGZO based TFTs with the limitations that, the device dimensions are not easily scalable. Besides, the Verilog-A model imposes restrictions as the analysis such as PVT (PreSure-Voltage-Temperature) analysis, corner analysis, and yield estimations are not possible using it.…”

Section: Introductionmentioning

confidence: 99%

Adaptation and comparative analysis of HSPICE level‐61 and level‐62 model for a‐IGZO thin film transistors

Dubey,

Goswami,

Kandpal

2024

Int J Numerical Modelling

View full text Add to dashboard Cite

This paper presents a Computer‐aided design (CAD) model for a‐IGZO thin film transistors (TFTs) by adapting SPICE level‐61 RPI a‐Si: H (Hydrogenated Amorphous Silicon) TFT model and level‐62 RPI Poly‐Si (Poly Silicon) TFT model. This work provides a complete understanding of SPICE level‐61 and 62 model parameters, which must be tuned for a‐IGZO TFT simulation. The adapted SPICE models of level‐61 and level‐62 could model all regions of operation of the TFT, that is, above‐threshold and below‐threshold regions. Adapted RPI poly‐Si model also shows the kink effect in ZnO thin film transistors (TFTs) due to the recombination of electron–hole pairs in the channel via boundary trap states present in the poly‐Si TFTs thereby increasing the drain current in the transistors above pinch‐off region. The extracted performance parameters of the adapted models were found to be contiguous with experimental results. The maximum deviation in the subthreshold slope is approximately 5 mV/decade for level‐61 a‐Si TFT, and for level‐62 poly‐Si TFT, deviation in the subthreshold slope is even less, that is, 0.2 mV/decade. The experimental and simulated characteristics, extracted on‐to‐off ratio, negative bias reverse saturation current, and threshold voltage were almost similar. However, an average deviation of 2.4% and 2.27% was observed in the output characteristics of the adapted level‐61 and level‐62 models, respectively.

show abstract

Adaptation of a compact SPICE level 3 model for oxide thin-film transistors

Kandpal

Gupta

2019

J Comput Electron

View full text Add to dashboard Cite

Physics-Based SPICE Model of a-InGaZnO Thin-Film Transistor Using Verilog-A

Cited by 6 publications

References 7 publications

Reliability-Aware SPICE Compatible Compact Modeling of IGZO Inverters on a Flexible Substrate

Reliability-Aware SPICE Compatible Compact Modeling of IGZO Inverters on a Flexible Substrate

Adaptation and comparative analysis of HSPICE level‐61 and level‐62 model for a‐IGZO thin film transistors

Adaptation of a compact SPICE level 3 model for oxide thin-film transistors

Contact Info

Product

Resources

About