Physics-based modeling of TID induced global static leakage in different CMOS circuits

Зебрев, Г. И.; Орлов, В. В.; Gorbunov, Maxim S.; Drosdetsky, Maxim G.

doi:10.1016/j.microrel.2018.03.014

Cited by 15 publications

(4 citation statements)

References 19 publications

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“…The proposed charge-controlled concept is similar to the work of Zebrev et al [34]. However, the work of Zebrev et al focuses on the inter-device parasitic leakage current underneath the STI oxide between the n-well of a pMOSFET and the source/drain of the nearby nMOSFET, whereas our work focuses on the intra-device parasitic leakage current along the STI sidewalls in parallel with the main n-type channel.…”

Section: B Utilization Of the Simplified Ekv Mosfet Modelmentioning

confidence: 85%

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

Zhang

Jazaeri

Borghello

et al. 2019

IEEE Trans. Nucl. Sci.

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This paper characterizes and models the effects of total ionizing dose (TID) up to 1 Grad(SiO2) on the drain leakage current of nMOSFETs fabricated with a commercial 28-nm bulk CMOS process. Experimental comparisons among individual nMOSFETs of various sizes provide insight into the TID-induced lateral parasitic devices, which contribute the most to the significant increase up to four orders of magnitude in the drain leakage current. We introduce a semi-empirical physicsbased approach using only three parameters to model the parallel parasitic and total drain leakage current as a function of TID. Taking into account the gate independence of the drain leakage current at high TID levels, we model the lateral parasitic device as a gateless charge-controlled device by using the simplified charge-based EKV MOSFET model. This approach enables us to extract the equivalent density of trapped charges related to the shallow trench isolation oxides. The adopted simplified EKV MOSFET model indicates the weak inversion operation of the lateral parasitic devices.

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Section: B Utilization Of the Simplified Ekv Mosfet Modelmentioning

confidence: 85%

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

Zhang

Jazaeri

Borghello

et al. 2019

IEEE Trans. Nucl. Sci.

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“…It only concerns N-Type transistors since the substrate is P-Type, and N-type parasitic canals can be formed on the STI walls. This leakage can be intra-component, between the source and the drain of the same transistor [11]; it can also be intercomponent, as a parasitic path of charge carriers can be formed on the STI connecting two MOS transistors, leading to an increase in the leakage current [12].…”

Section: Background a Tid Effectsmentioning

confidence: 99%

Simulation Methodology for Assessing X-Ray Effects on Digital Circuits

Tebina,

Zergainoh,

Hubert

et al. 2023

2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Recently, X-Rays have proven to be an interesting and feasible mean to perform fault injection attacks against secure implementations. Their wavelength allows targeting single elements even with most recent fabrication technologies, and their high penetration power does not demand to invasively prepare the device for the attack. Unlike operations in harsh environment, a malicious attacker can choose the targeted region at will, from a single cell up to large regions. This aspect forces designers to consider hardening against X-Rays under a different perspective. In this work, we will present a design-time simulation flow, that addresses how the electrical characteristics of the logic are changed when irradiated, from the perspective of injected faults and of biased power consumption.

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“…However, the continuous shrinking of CMOS channels has introduced a new concern, mostly caused by the charges trapped on the Shallow Trench Isolation (STI) oxides. These STI charges contribute to leakage currents in two ways: it can be intra-component (i.e., in the same transistor) [9] leakage that is between the source and the drain of the same transistor, also known as Radiation Induced Narrow Channel Effects (RINCE) [10]; it can also be inter-component (between two transistors), as a parasitic path of charge carriers can be formed on the STI connecting two MOS transistors, leading to an increase in the leakage current [11].…”

Section: A Tid Effects On Mos Circuitsmentioning

confidence: 99%

X-Ray Fault Injection: Reviewing Defensive Approaches from a Security Perspective

Tebina

Zergainoh

Maistri

2022

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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With the emergence of a novel fault injection technique based on nanofocused X-Ray beams, these attacks have been proven feasible even when using simple laboratory X-Ray sources. X-Rays can induce parametric shifts in MOS components, mostly at the level of oxides: if properly controlled, these shifts lead to reversible stuck-at faults. It is therefore established that X-Rays can indeed be considered a threat that needs to be addressed in the future when designing secure circuits. In this paper, we discuss how countermeasures issued from the state of the art can be exploited to mitigate or resist against this novel attack.

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Physics-based modeling of TID induced global static leakage in different CMOS circuits

Cited by 15 publications

References 19 publications

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

Simulation Methodology for Assessing X-Ray Effects on Digital Circuits

X-Ray Fault Injection: Reviewing Defensive Approaches from a Security Perspective

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