Physically Unclonable Functions Using Foundry SRAM Cells

Clark, Lawrence T.; Medapuram, Sai Bharadwaj; Kadiyala, Divya Kiran; Brunhaver, John

doi:10.1109/tcsi.2018.2873777

Cited by 11 publications

(11 citation statements)

References 20 publications

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“…As shown in Figure 7, the pass rates for all combinations are higher than 90%, and RC2 combinations of RC2-VD4 and RC2-VD5 show similar pass rates compared to the NIST recommended random data (NIST RND) [30]. Any bit bias for the entire bit strings of the PUF output can be checked using T1, T2 or T3 [11], which exhibits pass rates >0.95 for all combinations. However, the result of T4 shows that RC1 has more consecutive 1′s or 0′s than RC2.…”

Section: Randomnessmentioning

confidence: 87%

“…As can be seen in (11), the falling time at the time of discharging the RC2 is also slower than that of RC1 due to the second term in (11) when compared to (2) of the RC1. As expected, the output of the RC circuit changes according to the challenge bit pattern during the "transient-state."…”

Section: Rc Puf Simulationmentioning

confidence: 96%

“…There are various works related with PUFs, including delay-based PUF [1, [6][7][8][9], and memory-based PUF [10,11] over the past decade. Please refer to [6] for a comprehensive overview on PUFs.…”

Section: Introductionmentioning

confidence: 99%

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Design of Resistor-Capacitor Physically Unclonable Function for Resource-Constrained IoT Devices

Lee

Kang

et al. 2020

Sensors

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Keeping IoT devices secure has been a major challenge recently. One of the possible solutions to secure IoT devices is to use a physically unclonable function (PUF). A PUF is a security primitive that can generate device-specific cryptographic information by extracting the features of hardware uncertainty. Because PUF instances are very difficult to replicate even by the manufacturer, the generated bit sequence can be used as cryptographic keys or as a unique identifier for the device. Regarding the implementation of PUF, the majority of PUFs introduced over the past decade are in the form of active components and have been implemented as separate chips or embedded as a part of a chip, making it difficult to use them in low-cost IoT devices due to cost and design flexibility. One approach to easily adopt PUFs in resource-constrained IoT devices is to use passive components such as resistors and capacitors (RC) that can be configured at low cost. The main feature of this RC-based PUF is that it extracts the small difference caused by charging and discharging of RC circuits and uses it as a response. In this paper, we extend the previous research and show the possibility to secure IoT devices by using the RC-based PUF.

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Section: Randomnessmentioning

confidence: 87%

Section: Rc Puf Simulationmentioning

confidence: 96%

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Design of Resistor-Capacitor Physically Unclonable Function for Resource-Constrained IoT Devices

Lee

Kang

et al. 2020

Sensors

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“…Recent works have defined various classifications for PUFs that are based on how a PUF's intrinsic variations are exploited for the response bit generation. The most commonly used classes divide into bi-stable or delay-based PUFs [14][15][16][17][18][19][20][21]. Other works also target the class of analog-based PUF designs [22][23][24][25][26].…”

Section: Classification Of Pufsmentioning

confidence: 99%

Embedded Analog Physical Unclonable Function System to Extract Reliable and Unique Security Keys

et al. 2020

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Internet of Things (IoT) enabled devices have become more and more pervasive in our everyday lives. Examples include wearables transmitting and processing personal data and smart labels interacting with customers. Due to the sensitive data involved, these devices need to be protected against attackers. In this context, hardware-based security primitives such as Physical Unclonable Functions (PUFs) provide a powerful solution to secure interconnected devices. The main benefit of PUFs, in combination with traditional cryptographic methods, is that security keys are derived from the random intrinsic variations of the underlying core circuit. In this work, we present a holistic analog-based PUF evaluation platform, enabling direct access to a scalable design that can be customized to fit the application requirements in terms of the number of required keys and bit width. The proposed platform covers the full software and hardware implementations and allows for tracing the PUF response generation from the digital level back to the internal analog voltages that are directly involved in the response generation procedure. Our analysis is based on 30 fabricated PUF cores that we evaluated in terms of PUF security metrics and bit errors for various temperatures and biases. With an average reliability of 99.20% and a uniqueness of 48.84%, the proposed system shows values close to ideal.

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“…Process variation: Although SRAM cells are designed symmetrically, a cell initializes to a certain state at power up due to process variation and noise. Process variation leads to a mismatch between the two inverters in the SRAM cell and is the main source of randomness [11]. Process variation can be categorized into two sub-categories: global and local variation.…”

Section: Introductionmentioning

confidence: 99%

Modeling Static Noise Margin for FinFET based SRAM PUFs

Masoumian

Selimis

Maes

et al. 2020

2020 IEEE European Test Symposium (ETS)

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In this paper, we develop an analytical PUF model based on a compact FinFET transistor model that calculates the PUF stability (i.e. PUF static noise margin (PSNM)) for FinFET based SRAMs. The model enables a quick design space exploration and may be used to identify critical parameters that affect the PSNM. The analytical model is validated with SPICE simulations. In our experiments, we analyze the impact of process variation, technology, and temperature on the PSNM. The results show that the analytical model matches very well with the simulation model. From the experiments we conclude the following: (1) nFET variations have a larger impact on the PSNM than pFET (1.5% higher PSNM in nFET variations than pFET variations at 25°C), (2) high performance SRAM cells are more skewed (1.3% higher PSNM) (3) the reproducibility increases with smaller technology nodes (0.8% PSNM increase from 20 to 14 nm) (4) increasing the temperature from-10°C to 120°C leads to a PSNM change of approximately 1.0% for an extreme nFET channel length.

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Physically Unclonable Functions Using Foundry SRAM Cells

Cited by 11 publications

References 20 publications

Design of Resistor-Capacitor Physically Unclonable Function for Resource-Constrained IoT Devices

Design of Resistor-Capacitor Physically Unclonable Function for Resource-Constrained IoT Devices

Embedded Analog Physical Unclonable Function System to Extract Reliable and Unique Security Keys

Modeling Static Noise Margin for FinFET based SRAM PUFs

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