Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries

Abstract

In this work we propose a regular layout fabric practical for industrial random logic design and present cell synthesis algorithms specialized to this fabric. We show results on an industrial test-case where physical synthesis onto a library of extremely regular cells results in only 7% increase in leakage in comparison to traditional standard cells. We also show that using this fabric based cell synthesis system allows better overall area by allowing more upper layer routing. We achieve a 4% routable die size reduction by simultaneous cell synthesis and custom M1 routing.

A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing

“…1. The transistors are aligned in two diffusion strips (p and n), while polysilicon is laid out with vertical rectangles [5]. The diffusion strips can be isolated by connecting polysilicon gates to Vdd or Vss or by removing polysilicon and diffusion.…”

“…The work in [5] evaluated the impact of using a regular layout fabric in an industrial flow. Different algorithms for design automation were proposed to synthesize a small subset of cells.…”

Manufacturable nanometer designs using standard cells with regular layout

“…Efforts at Intel propose an approach to designing regular logic blocks using pre-generated layout templates [11] and using extremely regular diffusion structures extending the so-called Lithographers Dream Pattern paradigm [12]. The study by Talalay et al also proposes a possible definition for repeatable block and switch transistor logic model to describe functionality [11].…”

“…This will be important when automated means for managing layout complexity at small geometries are desired. The efforts of Ryzhenko et al [12], carried out in the more advanced 32-nm node, feature automatic cell synthesis onto the regular fabric and propose simultaneous cell synthesis and Metal1 routing resulting in area advantages, but incurring a small leakage penalty. In our work, we use Metal2 to complete internal cell connections in the extremely regular cells created for this study.…”

Area-Optimal Transistor Folding for 1-D Gridded Cell Design

“…For standard cell design, 1-D style implies an underlying active area with equally-spaced transistors and unidirectional metal layers routed on gridded layouts [17]. In this context, cell design is a problem that is moved from the continuous domain (any type of shape, any location) to the discrete domain (only rectangular shapes on a coarse grid with fixed pitch).…”