Physical Modeling for Programming of TANOS Memories in the Fowler–Nordheim Regime

Abstract

This paper presents a physics-based model that is able to describe the TANOS memory programming transients in the Fowler-Nordheim uniform tunneling regime across the bottom-oxide layer. The model carefully takes into consideration the trapping/detrapping processes in the nitride, the limited number of traps available for charge storage, and their spatial and energetic distribution. Results are in good agreement with experimental data on TANOS devices with different gate-stack compositions, considering a quite extended range of gate biases and times. The reduced gate-bias sensitivity of the programming transients with respect to the floating-gate cell is explained in terms of a finite number of nitride traps and a thinner extension of the nitride trapping region as the gate bias is increased. The model represents a valid contribution for the investigation of the achievable performances of the TANOS technology.

Semi-Analytical Model for the Transient Operation of Gate-All-Around Charge-Trap Memories

“…A reasonably good agreement appears, using the following parameters: N t = 5.3 × 10 19 cm −3 , σ n = 2 × 10 −12 cm 2 , σ r = 10 −12 cm 2 , ν 0 = 5 × 10 8 s −1 , and E T = 1.5 eV. Note that the mismatch between data and modeling results during programming at V G = 18 V can be attributed to a reduction of the trapping efficiency at large bias, as previously reported in [26], which is not included in the current model. Moreover, at the shortest times experimentally investigated in the figure, the possibility for spurious delays to compromise the pulse shape reaching device gate should be accounted for.…”

“…Once analytical solutions for the electrostatic and tunneling problems are known, the program transients of the GAA-CT cell can be calculated with the following equation [26]: (15) where N t is the trap density in the nitride (units: cm −3 ), σ n is the electron trapping cross section (units: cm 2 ), and e n is the Poole-Frenkel emissivity (units: s −1 ) from filled nitride traps…”

“…Here, ν 0 is the attempt-to-escape frequency from nitride filled traps (units: s −1 ), E T is the trap depth from the nitride conduction band, F n is the average electric field in the nitride, and β is the Poole-Frenkel coefficient [27]. Note that (15) assumes that all the empty nitride traps see the same tunneling current, i.e., it neglects both distributed trapping along the nitride thickness and electron transport in the nitride conduction band, which were shown to barely impact the program operation of planar cells [26]. As a consequence, traps are concentrated in the middle of the nitride, and conservation of J n leads to a correcting factor r bot /(r bot + t n /2) in (15).…”

“…8, where the trap emptying rates given by hole recombination (J p σ r n t /q) and electron emission (e n n t ) at the beginning of the erase transient (ΔV T = 6 V and V G = −12 V) are shown as a function of r 0 . Considering typical values of E T = 1.2−1.8 eV [14], [19], [26], electron emission appears as the dominant erase mechanism for large r 0 , while hole injection gains importance for small radii, due to the increase of F eq and J p . The value of r 0 marking the transition between the two mechanisms decreases as lower E T is considered, due to the larger emission rate given by (16).…”

Crystalline and liquid Si3N4characterization by first-principles molecular dynamics simulations

“…One of the most promising advanced memory for replacing the NVM-NAND architecture is the so called Charge Trapping Devices [1] based on the discrete trapping of electronic charge in the material defects: in general an amorphous Si 3 N 4 layer of few nanometer has been employed in the actual memory device preparation. Typically silicon nitride layer is deposited at high temperature (> 700 o C) by the help of Chemical Vapour Deposition technique with stoichiometric or Si-rich ratio obained by changing reactant gas flow rate.…”