Semi-Analytical Model for the Transient Operation of Gate-All-Around Charge-Trap Memories

Abstract

We present a detailed semi-analytical investigation of the transient dynamics of gate-all-around (GAA) chargetrap memories. To this aim, the Poisson equation is solved in cylindrical coordinates, and a modification of the well-known Fowler-Nordheim formula is proposed for tunneling through cylindrical dielectric layers. Analytical results are validated by experimental data on devices with different gate stack compositions, considering a quite extended range of gate biases and times. Finally, the model is used for a parametric analysis of the GAA cell, highlighting the effect of device curvature on both program/erase and retention. Index Terms-Charge-trap (CT) memories, Fowler-Nordheim (FN) tunneling, gate-all-around (GAA) memories, semiconductor device modeling.

Reliability of 3D NAND Flash Memories

“…Compared to the planar case, the electric field inside GAA-CT dielectrics is not constant, showing a maximum value at the substrate/tunnel oxide interface. This maximum value is about three times larger than the electric field in the tunnel oxide of the planar device: of course, this is a strong improvement for the programming dynamics [27]. In addition to that, the electric field in the GAA-CT blocking oxide is lower than in the planar case, thus resulting in a reduced electron leakage from the nitride to the gate during programming (see Fig.…”

“…Fig. 2.15 Comparison between a GAA-CT cell and a planar CT cell having the same thickness of the gate dielectrics in terms of energy-band profile (left) and electric field (right) during program, for V G = 12 V and neutral nitride [27] clearly shows a reduction of the thickness of the energy barrier which prevents electron tunneling from the substrate to the nitride. Compared to the planar case, the electric field inside GAA-CT dielectrics is not constant, showing a maximum value at the substrate/tunnel oxide interface.…”

“…This behavior enhances the hole tunneling current from the substrate to the nitride during erase. In addition, the lower electric field at the gate/blocking oxide interface prevents electron injection from the gate, thus relieving the erase saturation issues [27].…”

Applications of Nanotechnology in Next-Generation Nonvolatile Memories

“…The fine difference lies in the electrostatics of the multigate channel. From theoretical aspects, there have been a few modeling studies carried out of late on such multigate MOS NVM by Cho et al [43], Amorosso et al [126] and Sengupta et al [127]. These models are based on evaluating charge trapping and detrapping in the nitride trap/the nc states within the composite gate dielectric by applying the WKB approximation of quantum tunneling of electrons.…”

“…These models are based on evaluating charge trapping and detrapping in the nitride trap/the nc states within the composite gate dielectric by applying the WKB approximation of quantum tunneling of electrons. For this purpose, the surface potential of the MOSFET may be assumed fixed above a certain voltage as implemented in the models of Cho et al [43] and Amorosso et al [126] or it may be self-consistently evaluated with the charging of the floating gate/nc-embedded layer as performed by Sengupta et al [127] (Fig. 13).…”