Physical and electrical characteristics of high-κ gate dielectric Hf(1−x)LaxOy

Wang, X. P.; Li, M. F.; Chin, Albert; Zhu, Chunxiang; Shao, Jianda; Lu, Wu; Shen, Xiaojing; Xi, Yu; Ren, Chi; Chen, Shen; Huan, C. H. A.; Pan, J. S.; Du, An; Lo, Patrick; Chan, D.S.H.; Kwong, D. L.

doi:10.1016/j.sse.2006.05.008

Cited by 57 publications

(26 citation statements)

References 17 publications

(19 reference statements)

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“…On the contrary, there is a peak located at 2θ = 33.1°for the LaON film, suggesting its crystalline structure. This peak is in accordance with the (411) reflection of the cubic La 2 O 3 phase [15]. In addition, the thinner LaON film in the LaTiON/LaON stack (2 nm versus 4 nm for the sample with single LaON layer) usually needs a higher crystallization temperature for grain growth along the thickness dimension [8].…”

Section: Methodssupporting

confidence: 72%

LaTiON/LaON as band-engineered charge-trapping layer for nonvolatile memory applications

2012

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Charge-trapping characteristics of stacked LaTiON/LaON film were investigated based on Al/Al 2 O 3 / LaTiON-LaON/SiO 2 /Si (band-engineered MONOS) capacitors. The physical properties of the high-k films were analyzed by X-ray diffraction, transmission electron microscopy and X-ray photoelectron spectroscopy. The band profile of this band-engineered MONOS device was characterized by investigating the current-conduction mechanism. By adopting stacked LaTiON/LaON film instead of LaON film as charge-trapping layer, improved electrical properties can be achieved in terms of larger memory window (5.4 V at ±10-V sweeping voltage), higher program speed with lower operating gate voltage (2.1 V at 100-µs +6 V), and smaller charge loss rate at 125°C, mainly due to the variable tunneling path of charge carriers under program/erase and retention modes (realized by the band-engineered chargetrapping layer), high trap density of LaTiON, and large barrier height at LaTiON/SiO 2 (2.3 eV).

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Section: Methodssupporting

confidence: 72%

LaTiON/LaON as band-engineered charge-trapping layer for nonvolatile memory applications

2012

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“…38 It is now known to be due to a dipole layer of some sort and quite a low trapped charge density. 36 The La,Hf oxide system is also found to remain amorphous to quite high temperatures. 39,40 Nitridation to give HfLaON further raises the crystallization temperature.…”

Section: New Oxidesmentioning

confidence: 99%

“…These are found to have rather low defect densities and to suffer from less Fermi level pinning than HfO 2 itself. [35][36][37] Early studies of La 2 O 3 and Y 2 O 3 on Si found that they had a large negative flatband voltage shift, which was originally thought to be due to trapped charge. 38 It is now known to be due to a dipole layer of some sort and quite a low trapped charge density.…”

Section: New Oxidesmentioning

confidence: 99%

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Maximizing performance for higher K gate dielectrics

Robertson

2008

Journal of Applied Physics

138

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Further scaling of complementary metal oxide semiconductor gate stacks will require gate dielectrics with a higher dielectric constant (K) than HfO2. We point out that this will require strategies to minimize the overall effective oxide thickness of the gate stack, and not just maximizing the dielectric constant, so that the channel mobility is not impaired and there is still control of the flatband voltages. This may require retention of a SiO2-based interfacial layer, and attention should be paid to the flatband voltages of lanthanide oxides. Phase control of HfO2 and ZrO2 by addition of group IV elements offers simpler advances.

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“…Recently, there are promising reports on High-low-high barrier structure has shorter tunneling distance than low-high-low barrier structure. La 2 O 3 [9] and HfLaO film [10]. Considering benefits of high dielectric constant with reasonably high band offset of HfLaO film, we have first applied Hf (1Àx) La x O y film with different La concentrations to the IPD layer in replacement of middle Al 2 O 3 layer.…”

Section: Other Choices Of Materialsmentioning

confidence: 99%