2021
DOI: 10.1088/1361-6528/ac2dc5
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Photoinduced-reset and multilevel storage transistor memories based on antimony-doped tin oxide nanoparticles floating gate

Abstract: Recently, antimony-doped tin oxide nanoparticles (ATO NPs) have been widely used in the fields of electronics, photonics, photovoltaics, sensing, and other fields because of their good conductivity, easy synthesis, excellent chemical stability, high mechanical strength, good dispersion and low cost. Herein, for the first time, a novel nonvolatile transistor memory device is fabricated using ATO NPs as charge trapping sites to enhance the memory performance. The resulting organic nano-floating gate memory (NFGM… Show more

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Cited by 8 publications
(12 citation statements)
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“…Under the positive gate voltage and UV light irradiation, the C 12 -BTBT layer absorbs light to generate photo-excited holeelectron pairs, subsequently, the electrons are injected into the LUMO level of the PS layer under the gate electric field, so that the transfer curve of the transistor shifts more to the positive direction. [10,[61][62] According to the above experimental results, we conclude that after introducing charge trapping sites on the PS surface by plasma treatment, holes can be rapidly injected into PS in a short time to form surface electrets, which shifts the threshold voltage of the transistor to the negative direction, so that the transistor maintains high resistance state (i.e., low drain current) in a wide range of gate voltage. Nevertheless, the surface electret charges are sensitive to UV light and can be rapidly released under UV light irradiation, allowing the transistor to revert to a low resistance state (i.e., high drain current) within a certain gate voltage range.…”
Section: Resultsmentioning
confidence: 76%
See 1 more Smart Citation
“…Under the positive gate voltage and UV light irradiation, the C 12 -BTBT layer absorbs light to generate photo-excited holeelectron pairs, subsequently, the electrons are injected into the LUMO level of the PS layer under the gate electric field, so that the transfer curve of the transistor shifts more to the positive direction. [10,[61][62] According to the above experimental results, we conclude that after introducing charge trapping sites on the PS surface by plasma treatment, holes can be rapidly injected into PS in a short time to form surface electrets, which shifts the threshold voltage of the transistor to the negative direction, so that the transistor maintains high resistance state (i.e., low drain current) in a wide range of gate voltage. Nevertheless, the surface electret charges are sensitive to UV light and can be rapidly released under UV light irradiation, allowing the transistor to revert to a low resistance state (i.e., high drain current) within a certain gate voltage range.…”
Section: Resultsmentioning
confidence: 76%
“…Under the positive gate voltage and UV light irradiation, the C 12 ‐BTBT layer absorbs light to generate photo‐excited hole‐electron pairs, subsequently, the electrons are injected into the LUMO level of the PS layer under the gate electric field, so that the transfer curve of the transistor shifts more to the positive direction. [ 10,61–62 ]…”
Section: Resultsmentioning
confidence: 99%
“…In addition, the ultra-thin tunnel oxide layer in the nanocrystal floating-gate memory has the advantages of low power consumption and high erasing/programming speed [ 9 , 10 , 11 ]. The research on nanocrystal floating-gate memory is extensive, from traditional silicon germanium materials to third-generation semiconductor materials of SiC [ 15 , 16 , 17 ]. As reported by Jin et al [ 15 ], floating-gate memory based on antimony-doped tin oxide nanoparticles has a maximum memory window of 85 V. However, there are 40 program/erase cycles, which has not been tried in 3D NAND devices.…”
Section: Introductionmentioning
confidence: 99%
“…The research on nanocrystal floating-gate memory is extensive, from traditional silicon germanium materials to third-generation semiconductor materials of SiC [ 15 , 16 , 17 ]. As reported by Jin et al [ 15 ], floating-gate memory based on antimony-doped tin oxide nanoparticles has a maximum memory window of 85 V. However, there are 40 program/erase cycles, which has not been tried in 3D NAND devices. Lepadatu et al carried out research on a new floating-gate MOS structure consisting of an HfO 2 /floating gate of a single layer of Ge QDs in the HfO 2 /tunnel HfO 2 /p-Si wafers [ 16 ].…”
Section: Introductionmentioning
confidence: 99%
“…1–5 Benefitting mainly from the innovation of organic semiconductors (OSs) and the optimization of device engineering, the past several decades have witnessed amazing progress in the OSC field, highlighting the great potential of commercial application in the foreseeable future. 6–12 To be specific, the development of novel p-type OSs (donor materials) and n-type OSs (acceptor materials) has led to sufficient light absorption with minimum energy loss. 13–19 The strategies for device optimization, such as the use of ternary blends, layer-by-layer processing, and the use of solid additives, have also played an important role in fine-tuning the morphological characteristics of active layers, benefiting the charge separation and transport.…”
Section: Introductionmentioning
confidence: 99%