Phase locking scheme based on look-up-table-assisted sliding discrete Fourier transform for low-frequency power and acoustic signals

Evaluation of Quadrature Signal Generation Methods with Reduced Computational Resources for Grid Synchronization of Single-Phase Power Converters through Phase-Locked Loops

“…In analog PLLs, this block is a dedicated circuit controlled by the output voltage of the LF [3], but in the digital versions used in current power electronic converters, the controlled oscillator is realized with look-up tables (LUTs), the coordinate rotation digital computer (CORDIC) or the digitally controlled oscillator (DCO). The LUTs, as in [22], occupy large memory resources either implemented in a field-programmable gate array (FPGA) or in digital signal processors (DSP). The use of CORDIC algorithms [23] adds complexity and slows down the execution of PLL circuits.…”

Sliding discrete Fourier transform based frequency‐locked loop for adaptive carrier tracking of bi‐phase signals

“…For k = 1, the zero placed at z = r e j2 π / N is cancelled by a pole z = r e j2 π / N , so that the fundamental frequency is passed through the SDFT and all other harmonics are rejected including dc. The z ‐domain transfer functions of in‐phase and quadrature components [19] of (2) are Fig. 1 a realises (3) as a k th‐bin SDFT structure.…”

Voltage sag and swell mitigation based on modulated carrier PWM

“…At the nominal mains frequency of 50 Hz, it also provides a pulse-train at 25.6 kHz (=4 Â 128 Â 50), which is used for generating the triangular dither at 6.4 kHz [49]. The frequency of the triangular dither signal would naturally vary in tune with the wandering mains frequency, so that the number of divisions of the mains-sine-wave remains constant at 128, enabling the use of commonly available DSP algorithms [50]. This scheme is also programmed to give a unit sine wavev a ðtÞ, so that the compensation signal l A Á sin(xt) can be generated as shown in Fig.…”