Phase-change memory cycling endurance

Abstract

Abstract

Phase-change materials in electronics and photonics

“…Kim et al 56 focus on cycling endurance as a critical challenge that hinders further improvements in phase-change devices to rival DRAM. The current endurance limit is about 10 12 write-erase cycles, which must be improved to 10 15 or higher to meet the high-frequency memory requirements for data-intensive applications.…”

In situ TEM observation of void formation and migration in phase change memory devices with confined nanoscale Ge2Sb2Te5

“…[9][10][11][12][13] It has been reported that the endurance failure of GST-based PCMs is induced by material degradation caused by void formation (which leaves devices "stuck" in the reset state 14 ) or to a gradual segregation of the elemental Ge, Sb, and Te in different regions of the device. [15][16][17] It is believed that this segregation slowly alters the switching characteristics of the device. Although this can be advantageous initially, 18 eventually the original reset pulse is no longer sufficient to switch the device and this leads to a "stuck reset" failure.…”

“…To realize storage-class memory based on PCM technology, the device's cycling endurance should allow 10 15 -10 16 cycles. 17,19 Many modern GST-based PCM cell designs adopt a nanometer-scale conned cylinder as programing volume to increase the cell density and reduce the operation power. In contrast to the traditional PCM devices with a mushroomshaped programing volume, the modern PCM devices which conne GST into a nanopillar structure have shown to exhibit excellent reliability by achieving more than 10 12 programing cycles with dri and noise mitigation for multilevel cell operation.…”

Multilevel Switching in Phase‐Change Photonic Memory Devices

“…The reversible multilevel SET and RESET process using a high‐intensity single‐shot laser fluence have observed phase segregation of the individual atoms, affecting the endurance cycles of the phase‐change photonic memory devices. [ 67,68 ] Moreover, for realizing each optical level, the laser fluence needs to be precisely tuned, which increases the complexity of the switching process. Therefore, the single‐shot programming technique needs to be optimized to make it as the widely accepted programming technique for multilevel switching applications such as in‐memory computation.…”