Phase accumulated carrier pulse width modulation

Abstract

An alternative approach to digital PWM generation uses an accumulator rather than a counter to generate the carrier. This offers several advantages. The resolution and gain of the pulse width modulator remain constant regardless of the module clock frequency and PWM output frequency. The PWM resolution also becomes fixed at the register width. Even at high PWM frequencies, the resolution remains high when averaged over a number of PWM cycles. An inherent dithering of the PWM waveform introduced over successive cycles blurs the switching spectra without distorting the modulating waveform. The technique also lends itself to easily generating several phase shifted PWM waveforms suitable for multilevel converter modulation. Several example waveforms generated using both simulation and FPGA hardware are presented.

Synchronisation of a distributed control and data acquisition system for modular multi‐level PHIL amplifiers

“…A phase accumulation PWM (PACPWM) [5] block is implemented in the system (application) clock domain, using a 32‐bit accumulator (see Fig. 3).…”

Self‐organising technique for carrier synchronisation and phase offset distribution in modular, fault‐tolerant converters

“…The synchronisation module is based on a phase accumulated carrier pulse width modulator (PACPWM) [13], which uses a 32‐bit accumulator and 100 MHz clock to synthesise the carrier signal. Frequency is controlled via a 32‐bit phase increment word, providing very high average frequency precision.…”

FPGA implementation of an arbitrary resample rate, FOH, pulse width modulator

“…Phase accumulator carrier pulse‐width modulation (PACPWM) is an alternative approach to the conventional counter‐based PWM which is implemented in most microcontrollers [6]. PACPWM provides the advantage of decoupling the frequency resolution of the PWM from the amplitude resolution.…”