pGate: An Introduction to A Novel Universal Gate and Power Drop Calculation of QCA circuits

Roy, Santanu

doi:10.18535/ijecs/v6i4.31

Cited by 2 publications

(3 citation statements)

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“…Now this waveform also provides the same values, as given in table III. Hence this is to be concluded that the NAND gate is successfully designed by T gate methodology [17]- [19].…”

Section: A T Nand Gate Designingmentioning

confidence: 94%

“…S. A & B these two are the input data lines and correspondingly the Y denotes the output data line. The layout is designed in QCADesigner and simulated properly to express the output waveform of the multiplexer [16]- [19]. Fig.…”

Section: Proposed Multiplexer Designmentioning

confidence: 99%

“…Therefore, the with the help of inputs signal bit combination the output bit sequence is given as {00011011}. From the references, [3], [19] it is possible to configure a QCA circuit with partial polarizations. This partial polarization test is performed on the proposed 11 cells MUX.…”

Section: Optimized Area-delay Efficient Multiplexer Designmentioning

confidence: 99%

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A Novel Optimized Multiplexer Design in Quantum-Dot Cellular Automata

Roy¹

2017

IJRASET

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Molecular quantum-dot cellular automata (QCA) is an emerging nanocomputing paradigm, which operates on electrostatic repulsion phenomena between two electrons to keep those apart at the maximum distance to a rest position for obtaining the highest finding probability. In the field of Quantum-dot Cellular Automata the digital logic gate approaches nearly about to nanometer in scale. In QCA quantum gates operate by the tunneling effect of electrons from one quantum dot to another dot through revealing its wave nature. The operating speed of the device gains the speed of light because the quantum tunneling occurs at the light speed. This paper compares two methodologies of quantum logic gate designing, those are universal T gate designing and conventional gate designing practice. One 22 cells 2x1 MUX is proposed which is designed by conventional method, that provides 20.35% optimization in area occupancy compared to the best reported designs. Furthermore, one 11 cells 2:1 MUX layout is proposed which achieves 33.33% area reduction compared to the best ever multiplexer designed in QCA technology.

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“…Now this waveform also provides the same values, as given in table III. Hence this is to be concluded that the NAND gate is successfully designed by T gate methodology [17]- [19].…”

Section: A T Nand Gate Designingmentioning

confidence: 94%

Section: Proposed Multiplexer Designmentioning

confidence: 99%

See 1 more Smart Citation

A Novel Optimized Multiplexer Design in Quantum-Dot Cellular Automata

Roy¹

2017

IJRASET

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Implementation of Novel Binary Logic Gates with Temperature Stability Factor Analysis in Quantum-dot Cellular Automata

Roy¹

2018

JPMT

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Quantum-dot cellular automata is a molecular logic synthesis technology which is the utmost instance for the shift of microelectronics technology towards the molecular electronics. Nowadays the quantum-dot cellular automata has been playing a major role in the list of the most emerging quantum information computation techniques. Quantum-dot cellular automata is a nanoscale information computational technology which operates through the quantum bits that are temporarily created as a result of electron tunneling in between two qdots. This is an electron configuration based device which utilizes the electrostatic repulsive force to initialize a particular binary logic state based on electronic orientation inside quantum dots. In this paper a few novel methodologies for binary logic gate designing have proposed which are highly optimized in terms of area occupancy and clock latency. Using the proposed universal gates one adjoined half adder-half subtractor, 1 bit comparator and 2 to 1 multiplexer layouts have designed. Moreover, the temperature stability factor for the proposed circuits have also analyzed to reveal the dynamic errors of the circuits during its operation. This temperature stability factor asserts that both of the proposed circuits' adjoined adder-subtractor and the 1 bit comparator have the same operating range of temperature within 1 K to 6 K. Moreover, the cell wise power dissipation analysis for proposed gates has also performed to specify the input polarization strength limit.

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pGate: An Introduction to A Novel Universal Gate and Power Drop Calculation of QCA circuits

Cited by 2 publications

References 0 publications

A Novel Optimized Multiplexer Design in Quantum-Dot Cellular Automata

A Novel Optimized Multiplexer Design in Quantum-Dot Cellular Automata

Implementation of Novel Binary Logic Gates with Temperature Stability Factor Analysis in Quantum-dot Cellular Automata

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