Implementation of Novel Binary Logic Gates with Temperature Stability Factor Analysis in Quantum-dot Cellular Automata

Abstract

Quantum-dot cellular automata is a molecular logic synthesis technology which is the utmost instance for the shift of microelectronics technology towards the molecular electronics. Nowadays the quantum-dot cellular automata has been playing a major role in the list of the most emerging quantum information computation techniques. Quantum-dot cellular automata is a nanoscale information computational technology which operates through the quantum bits that are temporarily created as a result of electron tunneling in between two qdots. This is an electron configuration based device which utilizes the electrostatic repulsive force to initialize a particular binary logic state based on electronic orientation inside quantum dots. In this paper a few novel methodologies for binary logic gate designing have proposed which are highly optimized in terms of area occupancy and clock latency. Using the proposed universal gates one adjoined half adder-half subtractor, 1 bit comparator and 2 to 1 multiplexer layouts have designed. Moreover, the temperature stability factor for the proposed circuits have also analyzed to reveal the dynamic errors of the circuits during its operation. This temperature stability factor asserts that both of the proposed circuits' adjoined adder-subtractor and the 1 bit comparator have the same operating range of temperature within 1 K to 6 K. Moreover, the cell wise power dissipation analysis for proposed gates has also performed to specify the input polarization strength limit.