2015 2nd International Conference on Electronics and Communication Systems (ICECS) 2015
DOI: 10.1109/ecs.2015.7124762
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Performance study of high-k gate & spacer dielectric Dopant Segregated Schottky Barrier SOI MOSFET

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Cited by 4 publications
(2 citation statements)
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“…Using a high‐K for an orderly pile gate decreases the leakage current, enabling the transistors to scale down 20,21 . The low energy barrier created by SiO 2 can be also fastened by using the HfO 2, subsequently in higher drain currents 22 …”
Section: Introductionmentioning
confidence: 99%
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“…Using a high‐K for an orderly pile gate decreases the leakage current, enabling the transistors to scale down 20,21 . The low energy barrier created by SiO 2 can be also fastened by using the HfO 2, subsequently in higher drain currents 22 …”
Section: Introductionmentioning
confidence: 99%
“…20,21 The low energy barrier created by SiO 2 can be also fastened by using the HfO 2, subsequently in higher drain currents. 22 The high axial scaling bulges the issue of highly accelerated and energetic hot carriers. The electric field augmented these hot carriers in the channel to achieve sufficient energy to damage the Si-SiO 2 interface, degrading device performance.…”
Section: Introductionmentioning
confidence: 99%