Performance Improvement and Analysis of PtSi Schottky Barrier p-MOSFET Based on Charge Plasma Concept for Low Power Applications

Kale, Sumit

doi:10.1007/s12633-019-00161-1

Cited by 11 publications

(1 citation statement)

References 27 publications

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“…This level of loss is rather high and must be reduced for better reliability in operation. Hence, a more refined optimization or additional mitigation approaches, such as the introduction of an additional WF for one of the gate inputs [28], [29] to compensate or tune out such losses, may be necessary for more complex functions that require additional logic depth.…”

Section: Discussionmentioning

confidence: 99%

Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

Canan

Kaya

Kodi

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to ×10) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance. INDEX TERMS 3T-XOR, 4T AND-OR-invert (AOI), 6T 4-to-1 multiplexer (MUX), ambipolar, CMOS logic gates, nanotechnology, Schottky-barrier MOSFET, tunneling.

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Section: Discussionmentioning

confidence: 99%