Performance-preserved analog routing methodology via wire load reduction

Analog Integrated Circuit Routing Techniques: An Extensive Review

“…Additionally, tile-based grid-less routers [121][122] or even mixed A* and maze [123] were also reported. A* (and related) became a popular approach, and several works used it to deal with more routing challenges, such as minimum area [124] and step [125] constraints, wire load reduction [126]- [128], net shielding [123], parallel run and end-of-line spacings [125], etc. Recently, in MAGICAL (2019-2021) [173][174], A* search is used at both global and detailed routing phases.…”

Achieving analog layout integrity through learning and migration

“…When packing an SP, the routing demands resulting from routing path analysis based on the CDL model are added to the edges of both horizontal and vertical constraint graphs (HCG and VCG), as seen in Figure 11(b), as the edge weights. For the newly added net in the target design, we apply the routing method [4] to estimate the routing demands.…”