Performance optimization of error detection based on speculative reconfiguration

Lifa, Adrian; Eles, Petru; Peng, Zebo

doi:10.1145/2024724.2024812

Cited by 4 publications

(3 citation statements)

References 21 publications

(28 reference statements)

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“…In the first case, we propose hardware/software codesign techniques that leverage the advantages of partial dynamic reconfiguration of FPGAs in order to minimize the global worst-case schedule length of an application, while meeting the imposed hardware cost constraints and tolerating multiple transient faults [LEPI10]. In the latter case, we propose a technique to minimize the average execution time of a program by speculatively prefetching on the FPGA those error detection components that will provide the highest performance improvement [LEP11]. …”

Section: Summary Of Contributionsmentioning

confidence: 99%

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Lifa¹

2015

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M odern applications running on today's embedded systems have very high requirements. Most often, these requirements have many dimensions: the applications need high performance as well as flexibility, energyefficiency as well as real-time properties, fault tolerance as well as low cost. In order to meet these demands, the industry is adopting architectures that are more and more heterogeneous and that have reconfiguration capabilities. Unfortunately, this adds to the complexity of designing streamlined applications that can leverage the advantages of such architectures.In this context, it is very important to have appropriate tools and design methodologies for the optimization of such systems. This thesis addresses the topic of hardware/software codesign and optimization of adaptive real-time systems implemented on reconfigurable and heterogeneous platforms. We focus on performance enhancement for dynamically reconfigurable FPGA-based systems, energy minimization in multi-mode real-time systems implemented on heterogeneous platforms, and codesign techniques for fault-tolerant systems.The solutions proposed in this thesis have been validated by extensive experiments, ranging from computer simulations to proof of concept implementations on real-life platforms. The results have confirmed the importance of the addressed aspects and the applicability of our techniques for design optimization of modern embedded systems. v vi Populärvetenskaplig Sammanfattning I dag är inbyggda system vanligt förekommande och deras antal fortsätter att öka. De används inom en mängd olika domäner, t.ex. hemelektronik, fordonsindustri, flygelektronik, medicin, etc., och de hittas nästan överallt omkring oss: från våra telefoner, bärbara datorer och tvättmaskiner till våra bilar. De applikationer som körs på dessa system har flera olika ökande krav: högprestanda, energieffektivitet, flexibilitet, feltolerans, realtidsegenskaper, och naturligtvis låg kostnad. För att kunna uppfylla dessa krav har industrin anammat arkitekturer som är mer och mer heterogena och som har omkonfigureringsmöjligheter. Olyckligtvis ökar detta komplexiteten när man ska utforma effektiva inbyggda system. I detta sammanhang blir det av yttersta betydelse att utveckla effektiva optimeringsmetoder och verktyg.Dagens applikationer består av en blandning av mjukvarukomponenter som har mycket olika energi-och prestandaegenskaper beroende på vilka hårdvaruenheter där de körs på, vilket gör dem lämpliga för heterogena plattformar. En heterogen plattform består av olika typer av hårdvaruen-heter, var och en med sina egenskaper, som riktar sig till vissa tillämpn-ingsområden. Under det senaste decenniet har utvecklingen av rekonfigurerbara hårdvarutekniker accelererat, vilket bidrar till den ökande populariteten för fältprogrammerbara grindmatriser (FPGA). Idag, ger hård-varutillverkare stöd för partiell dynamisk omkonfigurering; detta innebär att delar av en FPGA kan konfigureras vid run-time, medan andra delar förblir fullt fungerande. Dessa tekniska framsteg har...

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Section: Summary Of Contributionsmentioning

confidence: 99%

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Lifa¹

2015

Self Cite

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“…The authors of [8] present an approach for accelerating the error detection mechanisms. A set of path-dependent prefetches are prepared at design time, and at run-time the appropriate action is applied, corresponding to the actual path taken.…”

Section: Related Workmentioning

confidence: 99%

Minimization of average execution time based on speculative FPGA configuration prefetch

Lifa

Eles

Peng

2012

2012 International Conference on Reconfigurable Computing and FPGAs

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One of the main drawbacks that significantly impacts the performance of dynamically reconfigurable systems (like FPGAs), is their high reconfiguration overhead. Configuration prefetching is one method to reduce this penalty by overlapping FPGA reconfigurations with useful computations. In this paper we propose a speculative approach that schedules prefetches at design time and simultaneously performs HW/SW partitioning, in order to minimize the expected execution time of an application. Our method prefetches and executes in hardware those configurations that provide the highest performance improvement. The algorithm takes into consideration profiling information (such as branch probabilities and execution time distributions), correlated with the application characteristics. Compared to the previous state-of-art, we reduce the reconfiguration penalty with 34% on average, and with up to 59% for particular case studies.

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“…If the failure is trapped in a feedback loop the logic must be reset to an initial state. [11] are concerned in the detection, localizing and recovering from the errors. Recovery is done usually by reconfiguring the FPGA totally or partially to correct the errors.…”

Section: Introductionmentioning

confidence: 99%

Transient and Permanent Adaptive Fault Classifier for FPGA Applications in the Space

Tawfeek¹,

Alkabani²,

Egila³

et al. 2018

IJCDS

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Field Programmable Gate Array devices (FPGAs) are used in many applications. FPGAs are subjected to faults especially in the space where they are subjected to radiation. Faults in FPGAs may be recoverable (transient) or non-recoverable (permanent). Recoverable faults can be resolved by reconfiguring the system, on the other hand non-recoverable faults, require the relocation of the logic to a non-faulty area. This paper proposes an adaptive fault classifier that can be used to differentiate fault types. The classification guides the system to use the suitable recovery strategy. Experimental results show the operation of the classifier and adaptation layers, the proposed classifier layer is smaller in area compared to previous work. The adaptation layer works satisfactory to cope with environment changes. Both of the layers work independently of the design on any other layer.

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Performance optimization of error detection based on speculative reconfiguration

Cited by 4 publications

References 21 publications

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Minimization of average execution time based on speculative FPGA configuration prefetch

Transient and Permanent Adaptive Fault Classifier for FPGA Applications in the Space

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