Performance of Quantized Min-Sum Decoding Algorithms for Irregular LDPC Codes

Oh, Daesun; Parhi, Keshab K.

doi:10.1109/iscas.2007.378624

Cited by 13 publications

(12 citation statements)

References 11 publications

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“…However, the simple structure of the variable node gives less space for improvement. For this reason, few studies [5,6] have considered the improvement of variable nodes. In [5], the variable node which receives soft information from channels was multiplied, with a correction item to improve the performance [3,4] executed in the irregular matrix.…”

Section: Introductionmentioning

confidence: 99%

“…For this reason, few studies [5,6] have considered the improvement of variable nodes. In [5], the variable node which receives soft information from channels was multiplied, with a correction item to improve the performance [3,4] executed in the irregular matrix. In [6], transform circuits were added to the length of quantization (Q-LLR) to reduce the bit number required in the algorithm, hence reducing the hardware area of the memory.…”

Section: Introductionmentioning

confidence: 99%

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Cost-effective variable node using thermalcode addition for LDPC decoders

Yang

Liu

2011

IEICE Electron. Express

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Abstract:The current paper presents thermalcode addition technology as applied to an LDPC decoder to replace a variable node unit in the traditional adder. The proposed irregular quantization of thermalcode addition can generate information with regularity, which makes addition to the variable node executable by combinational logic circuit. With the original BER performance, code rate 1/2, and matrix (1296,648) in 802.11n standard, the simulation and logic synthesis results reveal that the presented LDPC decoder can save up to 21% of the hardware area.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Cost-effective variable node using thermalcode addition for LDPC decoders

Yang

Liu

2011

IEICE Electron. Express

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“…If we can reduce one bit for each intrinsic (or extrinsic) message, the storage complexity can be significantly reduced. In [13] [14] [23], several quantization schemes were presented. In [13], the authors proposed using different quantization schemes at different signalto-noise ratios (SNRs) for intrinsic messages.…”

Section: Introductionmentioning

confidence: 99%

“…In [13], the authors proposed using different quantization schemes at different signalto-noise ratios (SNRs) for intrinsic messages. In [14][23], intrinsic messages are scaled down as the iteration number increases in order to compensate the quantization errors caused by finite precision. It is worth noting that both quantization schemes presented in [13] and [14] focused on the quantization of the intrinsic messages.…”

Section: Introductionmentioning

confidence: 99%

Adaptive quantization for low-density-parity-check decoders

Chung

Ueng

et al. 2010

2010 International Symposium on Information Theory &Amp; Its Applications

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For the implementation of low-density parity-check (LDPC) decoders, the associated error performance and the complexity are significantly affected by the number of quantization bits used. In this paper, we propose an adaptive quantization scheme, which uses different quantization schemes at different iteration numbers based on a fixed number of quantization bits. Simulation results show that the proposed adaptive quantization can reduce the number of quantization bits without error performance degradation.

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“…While this choice tends to produce a larger PE area with respect to minsum approaches, the decoding performances are improved, enabling less decoding iterations to be implemented. In particular, [29] showed how minsum performance tends to be degraded by fixed-point implementations and in presence of irregular codes. Starting from these considerations we expect our area occupation to be larger than the other ones.…”

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confidence: 99%

Design of a VLSI Decoder for Partially Structured LDPC Codes

Vacca

Dinoi

Masera

2008

International Journal of Digital Multimedia Broadcasting

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The starting point of this work is the development of a new class of partially structured LDPC codes, very well suited for hardware implementation. Specifically these codes are built so that the edges of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

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Performance of Quantized Min-Sum Decoding Algorithms for Irregular LDPC Codes

Cited by 13 publications

References 11 publications

Cost-effective variable node using thermalcode addition for LDPC decoders

Cost-effective variable node using thermalcode addition for LDPC decoders

Adaptive quantization for low-density-parity-check decoders

Design of a VLSI Decoder for Partially Structured LDPC Codes

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