Performance of Multiplierless FIR Filter based on CSD and Binary: A Comparative Study

Sajwan, N.; Kumar, Arun; Sharma, Ila; Balyan, L. K.

doi:10.1109/icsc45622.2019.8938282

Cited by 3 publications

(1 citation statement)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Moreover, there are also some works focusing on a hybrid filter structure for complexity reduction [10][11][12]. For the VLSI implementation of FIR filters with fixed coefficients, a multiplierless design is a more general technique to reduce the hardware and time complexities [13][14][15][16][17][18][19][20][21][22][23]. In the multiplierless implementation of FIR filters, the constant multiplications are generally implemented by optimized shift-add networks.…”

Section: Introductionmentioning

confidence: 99%

Multiplication and Accumulation Co-Optimization for Low Complexity FIR Filter Implementation

Rao

Lou

2022

Electronics

View full text Add to dashboard Cite

In multiplierless finite impulse response (FIR) filters, the product accumulation block (PAB) could be the major contributor to hardware complexity, especially for high-order filters. In this paper, an optimization scheme where the constant multiplication block and the PAB are jointly optimized at the bit-level is proposed to minimize the hardware complexity. In the proposed joint optimization, the multiple constant multiplications (MCM) block is rearranged into several MCM sub-blocks. The products are summed locally before accumulation to reduce the word-length of the structural adders. It is shown that the symmetric property of linear phase FIR filters can be utilized in some cases to further reduce the complexity of the constant multiplications. Quantitative analyses are also presented to study the relationship between the optimum group size and the coefficient values as well as the filter orders. It is shown that there is no fixed optimum structure for filters with different coefficient word-lengths and filter orders, and each filter needs to be optimized specifically to achieve the minimum hardware complexity. Implementation results are presented to validate the effectiveness of the proposed method.

show abstract