Area-Efficient VLSI Design for Fibonacci Q-matrix-based Cyber-Physical Systems using Canonical Signed Digit Recoding Methods with Modulo Reductions

Juang, Tso-Bing

doi:10.1109/ecice59523.2023.10383002

2023 IEEE 5th Eurasia Conference on IOT, Communication and Engineering (ECICE) 2023

DOI: 10.1109/ecice59523.2023.10383002

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Area-Efficient VLSI Design for Fibonacci Q-matrix-based Cyber-Physical Systems using Canonical Signed Digit Recoding Methods with Modulo Reductions

Tso-Bing Juang

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Area-Efficient VLSI Design for Fibonacci Q-matrix-based Cyber-Physical Systems using Canonical Signed Digit Recoding Methods with Modulo Reductions

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