Performance of FinFET based adiabatic logic circuits

Srilakshmi, K.; Tilak, A. V. N.; Rao, K. Ramakrishna

doi:10.1109/tencon.2016.7848456

Cited by 7 publications

(4 citation statements)

References 16 publications

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“…These components can then be used as part of a hybrid design, either with a conventional CMOS processor or with one of the other techniques discussed in this paper, to increase the overall efficiency of the system. The authors of [43] compare the performance and efficiency of four possible implementations of an adiabatic adder. For their tests, the authors simulated a four-bit adder in each of the four adiabatic logic families, and compared the adders based on their physical size in the layout and their power consumption at various frequencies.…”

Section: Adiabatic Computingmentioning

confidence: 99%

Survey of Novel Architectures for Energy Efficient High-Performance Mobile Computing Platforms

O’Connor,

Elfouly,

Alouani

2023

Energies

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There are many real-world applications that require high-performance mobile computing systems for onboard, real-time processing of gathered data due to latency, reliability, security, or other application constraints. Unfortunately, most existing high-performance mobile computing systems require a prohibitively high power consumption in the face of the limited power available from the batteries typically used in these applications. For high-performance mobile computing to be practical, alternative hardware designs are needed to increase the computing performance while minimizing the required power consumption. This article surveys the state-of-the-art in high-efficiency, high-performance onboard mobile computing, focusing on the latest developments. It was found that more research is needed to design high-performance mobile computing systems while minimizing the required power consumption to meet the needs of these applications.

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Section: Adiabatic Computingmentioning

confidence: 99%

Survey of Novel Architectures for Energy Efficient High-Performance Mobile Computing Platforms

O’Connor,

Elfouly,

Alouani

2023

Energies

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“…The circuit complexity in terms of number of devices and power clocks, reliability are the limitations of the secure adiabatic logic families. As there is minimum complexity and power dissipation, ECRL logic is chosen to implement the three-stage PPRM S-box [10]. The ECRL buffer/inverter shown in Fig.…”

Section: Adiabatic Logicmentioning

confidence: 99%

“…Among different logic families, FinFET based ECRL adiabatic logic is chosen as it offers better energy savings [10]. The prime objective of this work is to design energy efficient three-stage Positive Polarity Reed-Muller (PPRM) S-box.…”

Section: Introductionmentioning

confidence: 99%

Ultralow-Power and Secure S-Box Circuit Using FinFET Based ECRL Adiabatic Logic

Srilakshmi¹,

Tilak²,

Rao³

2018

JST

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Advanced Encryption Standard (AES) is the widely used technique in critical cyber security applications. In AES architecture S-box is the most important block. However, the power consumed by S-box is 75% of the total AES design. The S-box is also prone to Differential Power Analysis (DPA) attack which is one of the most threatening types of attacks in cryptographic systems. In this paper, a three-stage positive polarity Reed-Muller (PPRM) S-box is implemented with 45 nm FinFET using Efficient Charge Recovery Logic (ECRL) to reduce power consumption. The simulation results indicate up to 66% power savings for FinFET based S-box as compared to CMOS design. Further, the FinFET ECRL 8-bit S-box circuit is evaluated for transitional energy fluctuations and peak current traces to compare its resistance against side-channel attacks. The lower energy variations and uniform current trace exhibit the improved security performance of the circuit to withstand DPA and Differential Electromagnetic Radiation Attacks (DEMA).

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“…The use of FinFET as an alternative to CMOS further improves the energy recovery of the adiabatic logic. The performance comparison of different adiabatic circuits based on FinFET is analyzed with a Brent-Kung Adder as a test module [11].…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Adiabatic Vedic Multipliers

Kaza¹

2021

TURCOMAT

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Energy dissipation and reliability are the two important design constraints in the high performance processor design. With the advancements in the IC manufacturing and reduced feature sizes the energy dissipation increases in exponential manner at the lower technology nodes. So, there is a need to design energy-efficient and reliable circuits and systems. The reliability with temperature is also one of the major challenges in today’s smart systems as they are operated in harsh environments. Most of the works till date analyzed the reliability with respect to DC constraints. The basic operation in the high performance Digital Signal Processing (DSP) is the multiplication is used to simplify various operations like convolution, filtering and correlation. In this work, a Vedic multiplier with 4x4 size is implemented with FinFET based energy recovery Modified PFAL (MPFAL) logic at 45 nm technology node. The designed multiplier performance is analyzed and compared with our earlier work in terms of energy dissipation and delay. The results indicate a reduction of 55% in energy dissipation over ECRL based Vedic multiplier. Linear variation of power dissipation with temperature in the order of pW shows that design MPFAL Vedic muliplier is more reliable compared to CMOS multiplier.

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Performance of FinFET based adiabatic logic circuits

Cited by 7 publications

References 16 publications

Survey of Novel Architectures for Energy Efficient High-Performance Mobile Computing Platforms

Survey of Novel Architectures for Energy Efficient High-Performance Mobile Computing Platforms

Ultralow-Power and Secure S-Box Circuit Using FinFET Based ECRL Adiabatic Logic

Performance Analysis of Adiabatic Vedic Multipliers

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