Performance of C&lt;inf&gt;6&lt;/inf&gt;H&lt;inf&gt;8&lt;/inf&gt;O&lt;inf&gt;7&lt;/inf&gt;-treated and H- and Cl-passivated Ge-MOS-capacitances on Ge-virtual-substrate on Si(001)

Hanel, L. A.; Elogail, Yasmine; Schwarz, Daniel; Fischer, I. A.; Schulze, Jörg

doi:10.23919/mipro.2018.8400005

Cited by 1 publication

(2 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We used the surface roughness factor to fit the on state current (I ON ), indicating that an increase of I ON is achievable by further treatment of the Ge surface either during mesa etching or pre gate-oxide deposition. This is applicable through various passivation techniques [40][41][42]. Both experimental and simulation results (revealed by BTBT model) show an optimum doping concentration that leads to the best I ON /I OFF ratio (dependent on growth technique, the interface and bulk trap concentrations produced during processing).…”

Section: Resultsmentioning

confidence: 99%

“…This can be done by optimizing the etching process recipe. Concerning the D it , attention has been drawn to reduce it by finding a suitable cleaning and passivation steps equivalent to the Si standard cleaning processes prior to the oxide deposition step [42]. A main improvement is also achievable by extreme scaling down of device size that leads to almost bulk trap free nanowire structure geometry.…”

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si _x Ge_1–x–ySn _y heterostructure model for low power FET applications

Elogail

Fischer

Wendav

et al. 2018

Semicond. Sci. Technol.

View full text Add to dashboard Cite

High mobility materials are being studied to replace Si with the aim of enhancing the performance of nanoelectronic devices. Ge and III-V channels have recently received a lot of attention, where the combination of III-V channels in n-MOSFETs and Ge channels in p-MOSFETs integrated on Si substrates is regarded as a promising CMOS design. Ge integrated on Si is a very promising choice due to its superior transport properties and compatibility to CMOS technology. The main challenges faced by Ge-based FETs are the channel/gate interface quality, crystal defects due to integration on Si and the smaller bandgap compared to Si, which leads to elevated band-to-band-tunnelling leakage currents, setting limitations on the achievable off state current (I OFF ). In this work, we present results on the fabrication and characterization of vertical Ge-based p-channel planar doped barrier FET together with a simulation model based on extracted material data from our experimental work and literature. Based on the model, a design of a modified device using both planar doping and a heterostructure in the channel is presented. The channel engineered design uses a Ge/Si x Ge 1-x-y Sn y heterostructure, which is lattice matched to Ge, within the channel at different positions. The results show improved performance; the larger bandgap of the ternary alloy Si x Ge 1-x-y Sn y compared to Ge leads to a suppression of the I OFF as well as a reduced subthreshold swing, making the heterostructure device promising for energy efficient FET applications.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si _x Ge_1–x–ySn _y heterostructure model for low power FET applications

Elogail

Fischer

Wendav

et al. 2018

Semicond. Sci. Technol.

View full text Add to dashboard Cite

show abstract

Performance of C<inf>6</inf>H<inf>8</inf>O<inf>7</inf>-treated and H- and Cl-passivated Ge-MOS-capacitances on Ge-virtual-substrate on Si(001)

Cited by 1 publication

References 9 publications

Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si _x Ge_1–x–ySn _y heterostructure model for low power FET applications

Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si _x Ge_1–x–ySn _y heterostructure model for low power FET applications

Contact Info

Product

Resources

About

Performance of C<inf>6</inf>H<inf>8</inf>O<inf>7</inf>-treated and H- and Cl-passivated Ge-MOS-capacitances on Ge-virtual-substrate on Si(001)

Cited by 1 publication

References 9 publications

Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si x Ge1–x–y Sn y heterostructure model for low power FET applications

Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si x Ge1–x–y Sn y heterostructure model for low power FET applications

Contact Info

Product

Resources

About

Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si _x Ge_1–x–ySn _y heterostructure model for low power FET applications

Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si _x Ge_1–x–ySn _y heterostructure model for low power FET applications