Second International Conference on the Quantitative Evaluation of Systems (QEST'05) 2005
DOI: 10.1109/qest.2005.29
|View full text |Cite
|
Sign up to set email alerts
|

Performance modeling and architecture exploration of network processors

Abstract: This paper proposes a Petri net model for a commercial network processor (Intel IXP architecture) which is a multithreaded multiprocessor architecture. We consider and model three different applications viz., IPv4 forwarding, Network Address Translation, and IP Security running on IXP 2400/2850. A salient feature of the Petri net model is its ability to model the application, architecture and their interaction in great detail. The model is validated using the Intel proprietary tool (SDK 3.51 for IXP architectu… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1
1

Citation Types

1
17
0

Year Published

2007
2007
2009
2009

Publication Types

Select...
5
1

Relationship

3
3

Authors

Journals

citations
Cited by 9 publications
(18 citation statements)
references
References 19 publications
1
17
0
Order By: Relevance
“…This allows us to model the bank conflicts during DRAM access. Unlike the model in [9], the Petri net model handles packets of different lengths. We model the cell based interface for receiving and transmitting packets (described in Section 2.1.1), the SRAM and scratchpad memories and the buses connecting them to the MEs.…”
Section: Ipv4 Forwarding Petri Net Modelmentioning
confidence: 99%
See 4 more Smart Citations
“…This allows us to model the bank conflicts during DRAM access. Unlike the model in [9], the Petri net model handles packets of different lengths. We model the cell based interface for receiving and transmitting packets (described in Section 2.1.1), the SRAM and scratchpad memories and the buses connecting them to the MEs.…”
Section: Ipv4 Forwarding Petri Net Modelmentioning
confidence: 99%
“…Accessing it, results in a narrow access of 24 bytes 1 . Govind, et al [9] propose storing the header in the SRAM in an effort to reduce the fully saturated DRAM utilization. We observe that the packet header is accessed multiple times and exhibits certain amount of locality.…”
Section: Header Buffering (Hb)mentioning
confidence: 99%
See 3 more Smart Citations