P-Ware: A precise and scalable component-based simulation tool for embedded multiprocessor industrial applications

Assayad,; Yovine, Sergio

doi:10.1109/dsd.2007.4341467

Cited by 6 publications

(9 citation statements)

References 12 publications

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“…In this paper we will extend this technique and show how to apply it to the tasks model, and we will focus on presenting the methodology for synthesizing and exploring software-level and hardware-level schedulers by using the technique for constraints generation and P-WARE tool [23] for simulation-driven performance evaluation.…”

Section: Our Approachmentioning

confidence: 99%

“…Basics of software/hardware models and a compositional constraint generation technique for concurrent loops are presented in previous work [21][22][23] and [24] respectively. In this paper we will extend this technique and show how to apply it to the tasks model, and we will focus on presenting the methodology for synthesizing and exploring software-level and hardware-level schedulers by using the technique for constraints generation and P-WARE tool [23] for simulation-driven performance evaluation.…”

Section: Our Approachmentioning

confidence: 99%

“…The full component blocks semantics is given in [22,23]. The principal component details are also given in what follows.…”

Section: Hw Modelmentioning

confidence: 99%

“…In the opposite of the two first transactions, addition and multiplication must be executed on different cycles. References [22,23] give detailed presentations on the modeling of hardware architectures.…”

Section: Efficiencymentioning

confidence: 99%

“…In this example, it is necessary to take into account latencies due to the cyclic dependencies, not shown in the listing, between tasks, i.e., those due to the task reading the variable i and the task which decrements it on the one hand, and the reading/writing of variables M on the other hand. Finally, P-WARE [22,23,25] is used to evaluate the performance of global scheduling of the system (rate, bandwidth, execution time, etc.). A sequential scheduling has an execution time of six cycles and give a rate of one output every six cycles, whereas pipeline scheduling on two processors P1 and P2 produces a better rate for the same execution time as shown in Table 6.…”

Section: Efficiencymentioning

confidence: 99%

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A scheduler synthesis methodology for joint SW/HW design exploration of SoC

Assayad

Yovine

2010

Des Autom Embed Syst

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The introduction of high-performance applications such as multimedia applications into SoCs led the manufacturers to provide embedded SoCs able to offer an important computing power which makes it possible to answer the increasing requirements of future evolutions of these applications. One of the adopted solutions is the use of multiprocessor SoCs. In this paper, we present a joint SW/HW design exploration methodology for multiprocessor SoCs. The system model relies on transaction-level component-based models for modeling parallel software and multiprocessor hardware. Our proposal comprises two original points. First, we propose a composable software-level scheduler constraints synthesis technique. Second, we present a combined software-level and exploratory hardwarelevel schedulers. The methodology has the advantage of combining real-time requirements of software with effective exploitation of multiprocessor hardware. We describe and apply the methodology to synthesize a scheduler of a slice-based MPEG-4 video encoder on the multiprocessor Cake SoCs.

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Section: Our Approachmentioning

confidence: 99%