Performance Investigation of Various SRAM Cells for IoT Based Wearable Biomedical Devices

Kumar, Jayant; C, Ganesh Babu; Balaji, V.; Priyadharsini, K.; Karthi, S.

doi:10.1007/978-981-15-7345-3_49

Cited by 24 publications

(3 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Internet-of-Things (IoT) and biomedical devices, such as smart dust sensors and implants, have experienced significant advancements due to nanoscale integration in recent years [1]- [4]. These compact electronic systems, however, face a challenge in incorporating traditional batteries due to their miniature size, leading to limited energy capacity and quick depletion of stored power.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

On the Feasibility of Cascode and Regulated Cascode Amplifier Stages in ULV Circuits Exploiting MOS Transistors in Deep Subthreshold Operation

Della Sala,

Centurelli,

Monsurró

et al. 2024

IEEE Access

View full text Add to dashboard Cite

In the last years several ultra-low voltage (ULV) operational transconductance amplifiers (OTAs) with supply voltages below 0.5V have been proposed in the literature. To achieve high gain, multistage amplifiers are frequently exploited, in spite of the complexity of design and compensation approaches, whereas cascode and regulated-cascode OTA topologies have rarely been exploited to implement ULV amplifiers. On the other hand, most ULV amplifiers are designed for IoT and biomedical applications in which reducing power consumption is the most important specification, and MOS devices are operated in the subthreshold region. This paper focuses on exploiting the subthreshold operating region to design ULV single-stage OTAs that utilize an output cascoded branch to increase the equivalent output resistance and, consequently, the overall voltage gain. A detailed analytical study of the conditions for triode and saturation regions for MOS devices operating in deep subthreshold region is presented to demonstrate that, for an appropriate choice of the inversion coefficient (IC), a cascode configuration exhibits higher gain than a single transistor, for the same voltage overhead, even in ULV conditions. More specifically, the results presented in this work demonstrate that 4 MOS devices (2 NMOS and 2 PMOS) can be reliably stacked to build a complementary cascode amplifier, even with a supply voltage as low as 0.4V. We also present a novel topology of regulated-cascode amplifier suitable to be operated with a supply voltage of 0.4V and a voltage gain approaching 100dB. Simulation results referring to a 180nm CMOS technology and including PVT and mismatch variations confirm state-of-the-art performances, as well as the good robustness of the proposed regulated-cascode ULV OTA.

show abstract

Section: Introductionmentioning

confidence: 99%

“…1,2,3,4 . The gate terminals of transistors M p 1,3 are exploited to accurately set the bias current in the two branches (V bp1 voltage is set through a biasing current mirror, not shown), thus guaranteeing a stable transconductance gain (set by gmb n,p ) and therefore a stable gain-bandwidth product (GBW).…”

mentioning

confidence: 99%

On the Feasibility of Cascode and Regulated Cascode Amplifier Stages in ULV Circuits Exploiting MOS Transistors in Deep Subthreshold Operation

Della Sala,

Centurelli,

Monsurró

et al. 2024

IEEE Access

View full text Add to dashboard Cite

show abstract

“…[ 2,3 ] Owing to the demand for high‐speed data storage or transfer in wearable devices, applications of CMOS (Complementary Metal‐Oxide‐Semiconductor) and SRAM (Static Random‐Access Memory) in wearable devices have often been proposed. [ 4–6 ] Nevertheless, several challenges remain in the evolution of flexible electronics, including the selection of the buffer layer, construction of the active layer, and degradation of the devices after bending. The low‐temperature environment is required for the processes mentioned above when conducting the experiment; otherwise, the flexible substrate will be damaged during high‐temperature processing.…”

Section: Introductionmentioning

confidence: 99%

Design on Formation of Nickel Silicide by a Low‐Temperature Pulsed Laser Annealing Method to Reduce Contact Resistance for CMOS Inverter and 6T‐SRAM on a Wafer‐Scale Flexible Substrate

Hsu,

Chen,

Shieh

et al. 2023

Adv Elect Materials

View full text Add to dashboard Cite

A pulsed laser annealing method is utilized to directly synthesize nickel silicide (NiSi) as a contact material to improve the contact of electric devices. Three laser wavelengths, 355 nm (ultraviolet laser), 532 nm (green laser), and 1064 nm (infrared laser), are used for the NiSi synthesis during the pulsed laser annealing process. A NiSi phase with low sheet resistance is formed by an ultraviolet laser annealing (ULA) process without damaging the polyimide (PI) substrate. With the integration of the ULA process‐induced NiSi into p‐nnel MOSFET (PMOS) and n‐channel MOSFET (NMOS) devices, the on/off ratio improves significantly, and the field‐effect mobility increases by 30% because of the reduction in contact resistance from 21 to 8.5 kΩ. In addition to the PMOS and NMOS, the gains of the CMOS inverter at different Vdd values are improved by at least 30%. Moreover, the static noise margin of 6T‐SRAM is elevated from 0.82 to 1 V at Vdd = 4 V. The ability of the ULA process to synthesize a high‐quality NiSi layer on a flexible substrate is demonstrated. The integration of NiSi into electrical devices offers a new pathway for improving the electrical behavior of flexible devices.

show abstract

Error Correction Scheme with Decimal Matrix Code for SRAM Emulation TCAMs

Balne

Gowri

2022

Smart Innovation, Systems and Technologies

View full text Add to dashboard Cite

Performance Investigation of Various SRAM Cells for IoT Based Wearable Biomedical Devices

Cited by 24 publications

References 10 publications

On the Feasibility of Cascode and Regulated Cascode Amplifier Stages in ULV Circuits Exploiting MOS Transistors in Deep Subthreshold Operation

On the Feasibility of Cascode and Regulated Cascode Amplifier Stages in ULV Circuits Exploiting MOS Transistors in Deep Subthreshold Operation

Design on Formation of Nickel Silicide by a Low‐Temperature Pulsed Laser Annealing Method to Reduce Contact Resistance for CMOS Inverter and 6T‐SRAM on a Wafer‐Scale Flexible Substrate

Error Correction Scheme with Decimal Matrix Code for SRAM Emulation TCAMs

Contact Info

Product

Resources

About