Performance investigation of InAs based dual electrode tunnel FET on the analog/RF platform

Anand, Sunny; Sarin, R. K.

doi:10.1016/j.spmi.2016.06.001

Cited by 26 publications

(4 citation statements)

References 24 publications

(15 reference statements)

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“…Thus, a lot of research work has been carried out to improve its ON-state current using various device architectures [1][2][3][4][5][6][7][8][9][10][11][12]. Moreover, compound semiconductor materials have also been employed due to their smaller bandgap and higher mobility that can also be used in diversified structures to exploit both the material properties and device architectures to further enhance the performance of TFETs [13][14][15][16][17]. The use of high-k oxides strengthens the gate control over the channel, resulting in an enhanced performance of the devices.…”

Section: Introductionmentioning

confidence: 99%

Suppression of P-I-N forward leakage current in tunnel field-effect transistor

Ahmad¹,

Alam

Ahmad³

2023

Semicond. Sci. Technol.

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In this paper, we propose an architecture of Tunnel Field Effect Transistor (TFET) for suppression of the P-I-N forward leakage current. P-I-N forward leakage current is attributed to drift-diffusion mechanism under the forward bias condition; thereby gate loses all itscontrol over channel. In the proposed device architecture, source region bifurcated into sub-regions (referred to as P+ and P++) with different p-type doping concentrations. We haveintroduced electrostatic source (ES) electrode over oxide which encapsulates the low doped(P+) source region. ES is shorted to source electrode which means if the voltage at source terminal becomes positive, ES also turns positive causing decrement in P+ characteristics inthe source region. On the other hand, increment in voltage, P+ source region starts to become intrinsic region thus minimizing the chances of P-I-N diode getting forward biased. In the proposed device architecture along with variation of ES (Electrostatic Source) work function,P-I-N forward leakage current has been suppressed by 3 to 6 orders of magnitude at the cost of ON state current loss of 3 to 10 fold of magnitude. Considering the detrimental impact of P-I-N forward leakage current in circuits, this small penalty on the part of ON state current is worth accepting for significant reduction in parasitic P-I-N forward leakage current. We believe that the proposed technique will pave way for wide spread use of TFET in logic circuits.

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Section: Introductionmentioning

confidence: 99%

Suppression of P-I-N forward leakage current in tunnel field-effect transistor

Ahmad¹,

Alam

Ahmad³

2023

Semicond. Sci. Technol.

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“…The Tunnel Field Effect Transistor (TFET) is a promising candidate as its drain current depends on charge carriers tunneling through the potential barrier between source valence band and channel conduction band [6]. TFET has the advantages of lower leakage current, lesser power consumption and better immunity against SCEs [7]. Moreover, TFET can achieve SS values below 60 mV/ decade due to its tunneling mechanism rather than thermionic emission [6].…”

Section: Introductionmentioning

confidence: 99%

A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps

Elnaggar

Shaker

Fedawy

2019

Semicond. Sci. Technol.

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In this paper, we have investigated the effect of gate underlap, while using semiconducting silicide material as a source region, on the ambipolar and high-frequency performance of Tunnel Field Effect Transistors (TFETs). We demonstrated how to suppress the ambipolar conduction and enhance the ON current without deteriorating the performance of high-frequency switching characteristics of the double gate TFET by using the combined two methods. The ON to OFF current ratio (I ON /I OFF ) and subthreshold swing (SS) as figures of merit for DC performance have been investigated. The main analog performance parameters like the transconductance (g m ) and unit-gain cutoff frequency ( f T ) are analyzed. Moreover, circuit level digital performance parameters like the fall propagation delay (t phl ) and overshoot voltage (V p ) are inspected when the proposed design is utilized in an inverter circuit. Impact of effective oxide thickness and traps arising from manufacturing process on DC, analog, and circuit level performance is also investigated. TCAD simulation results reveal a significant enhancement in DC, analog and digital performance parameters of the proposed heterojunction TFET over Si-TFET that makes the proposed design more advantageous in the field of analog and digital applications.

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“…In this regard, Tunnel Field-effect Transistors (TFETs), that incorporate the mechanism of BTBT for current conduction, have gained a lot of attention as a viable substitute of traditional MOSFET in analog/RF and low-power applications due to its distinctive property of achieving sub-60 mV decade −1 of subthreshold swing (SS), compatibility with existing CMOS technology and substantial immunity against the short-channel effects. [2][3][4][5][6][7][8] Low SS indicates a sharp transition between OFF-and ON-states, which in turn allows for further downscaling of power supply to make TFETs more suitable in low power applications. However, besides all these benefits, TFETs endure from ambipolar conduction and substantially low ON-state current due to its P-i-N structure and input tunneling interface behaving like band-pass filter, respectively.…”

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confidence: 99%

Performance Investigation of a Vertical TFET with Inverted-T Channel for Improved DC and Analog/Radio-Frequency Parameters

Das

Pandey

2023

ECS J. Solid State Sci. Technol.

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A novel line tunneling based gate-on-source-only tunnel field-effect transistor (TFET) with inverted T-shaped channel (ITGOSO-VTFET) is proposed and investigated using a Synopsis TCAD 2-D simulator. The GOSO configuration along with dual counter-doped pockets (CDP) improve the ON-state current by enhancing the tunneling rate of charge carriers at source/channel interface while inverted T-shaped channel helps the proposed device in reducing the OFF-state (I_OFF) and ambipolar (I_AMB) currents. In comparison with double-gate (DG) and GoSo-CDP TFET, the order of I_OFF (I_AMB) in ITGOSO-VTFET are found to be improved by ~6 (~4) and ~7(~3), respectively. Furthermore, the impact of varying design parameters is analyzed to obtain the optimized performance of the proposed device. Apart from improvement in DC performance, ITGOSO-VTFET is also found to offering a much better analog/radio-frequency performance in terms of various parameters like g_m, f_T, TFP, GBP, and τ, which eventually makes the proposed device more suitable for low power and high-speed applications

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Performance investigation of InAs based dual electrode tunnel FET on the analog/RF platform

Cited by 26 publications

References 24 publications

Suppression of P-I-N forward leakage current in tunnel field-effect transistor

Suppression of P-I-N forward leakage current in tunnel field-effect transistor

A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps

Performance Investigation of a Vertical TFET with Inverted-T Channel for Improved DC and Analog/Radio-Frequency Parameters

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