Performance improvement of the memory hierarchy of RISC-systems by application of 3-D technology

Kleiner, M.B.; Kühn, Stefan; Ramm, Peter; Weber, W.

doi:10.1109/96.544361

Cited by 37 publications

(12 citation statements)

References 23 publications

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“…Many different uses of 3-D integration have been proposed, from stacking additional memory or extra levels of cache [10,34,43,24,47,20,19] to stacking multiple processors [6]. These two examples exploit the full advantages of 3-D chips, as attaching additional memory can provide lower latency compared to off-chip memory, and power can be saved because driving TSVs requires less power than long off-chip wires.…”

Section: Applications Of 3-d Integrationmentioning

confidence: 99%

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors

Valamehr

Huffmire

Irvine

et al. 2012

Cryptography and Security: From Theory to Applications

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3-D integration presents many new opportunities for architects and embedded systems designers. However, 3-D integration has not yet been explored by the cryptographic hardware community. Traditionally, crypto coprocessors have been implemented as a separate die or by utilizing one or more cores in a chip multiprocessor. These methods have their drawbacks and limitations in terms of tamper-resistance, side-channel immunity and performance. In this work we propose a new class of co-processors that are "snapped-on" to the main processor using 3-D integration, and we investigate their security ramifications. These 3-D co-processors hold many advantages over previous implementations. This paper begins with an overview of 3-D integration and its prior applications. We then outline security threat models relevant to crypto co-processors and discuss the advantages and disadvantages of using a dedicated 3-D crypto co-processor compared to traditional, commodity, off-chip crypto co-processors. We also discuss the performance improvements that can be gained from using a 3-D approach.

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Section: Applications Of 3-d Integrationmentioning

confidence: 99%

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors

Valamehr

Huffmire

Irvine

et al. 2012

Cryptography and Security: From Theory to Applications

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“…Already in 1996, [4] assessed the performance benefits of tightly integrating DRAMs in a 3D RISC system. By alleviating typical limitations on memory size and bandwidth, they estimated that performance benefits of up to 25% could be realized.…”

Section: B Stacking Memorymentioning

confidence: 99%

System-level power/performance evaluation of 3D stacked DRAMs for mobile applications

Facchini

Carlson

Vignon

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Convergence of communication, consumer applications and computing within mobile systems pushes memory requirements both in terms of size, bandwidth and power consumption. The existing solution for the memory bottleneck is to increase the amount of on-chip memory. However, this solution is becoming prohibitively expensive, allowing 3D stacked DRAM to become an interesting alternative for mobile applications. In this paper, we examine the power/performance benefits for three different 3D stacked DRAM scenarios. Our high-level memory and Through Silicon Via (TSV) models have been calibrated on state-of-theart industrial processes. We model the integration of a logic die with TSVs on top of both an existing DRAM and a DRAM with redesigned transceivers for 3D. Finally, we take advantage of the interconnect density enabled by 3D technology to analyze an ultra-wide memory interface. Experimental results confirm that TSV-based 3D integration is a promising technology option for future mobile applications, and that its full potential can be unleashed by jointly optimizing memory architecture and interface logic.

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“…Recent studies have provided block models for various architectural structures, including 3D caches [Tsai et al 2005;Reinman et al 2000;Kleiner et al 1996;Ronnen et al 2001], register files [Tremblay et al 1995], 3D arithmetic units Loh 2007, 2006b], and instruction schedulers [Puttaswamy and Loh 2006c], along with 2D-based placement tools such as Xie et al [2006]. However, most of these models are limited to folding blocks by wordlines or bitlines.…”

Section: Introductionmentioning

confidence: 99%

Investigating the effects of fine-grain three-dimensional integration on microarchitecture design

Liu

Kursun

et al. 2008

J. Emerg. Technol. Comput. Syst.

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In this article we propose techniques that enable efficient exploration of the 3D design space, where each logical block can span more than one silicon layer. Fine-grain 3D integration provides reduced intrablock wire delay as well as improved power consumption. However, the corresponding power and performance advantage is usually underutilized, since various implementations of multilayer blocks require novel physical design and microarchitecture infrastructure to explore 3D microarchitecture design space. We develop a cubic packing engine which can simultaneously optimize physical and architectural design for efficient vertical integration. This technique selects the individual unit designs from a set of single-layer or multilayer implementations to get the best microarchitectural design in terms of performance, temperature, or both. Our experimental results using a design driver of a high-performance superscalar processor show a 36% performance improvement over traditional 2D for 2-4 layers and 14% over 3D with single-layer unit implementations. Since thermal characteristics of 3D integrated circuits are among the main challenges, thermal-aware floorplanning and thermal via insertion techniques are employed to keep the peak temperatures below threshold.

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Performance improvement of the memory hierarchy of RISC-systems by application of 3-D technology

Cited by 37 publications

References 23 publications

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors

System-level power/performance evaluation of 3D stacked DRAMs for mobile applications

Investigating the effects of fine-grain three-dimensional integration on microarchitecture design

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