Performance-impact limited area fill synthesis

Abstract

Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local layout density. To improve manufacturability and performance predictability, area fill features are inserted into the layout to improve uniformity with respect to density criteria. However, the performance impact of area fill insertion is not considered by any fill method in the literature. In this paper, we first review and develop estimates for capacitance and timing overhead of area fill insertions. We then give the first formulations of the Performance Impact Limited Fill (PJL-Fill) problem with the objective of either minimizing total delay impact (MDFC) or maximizing the minimum slack of all nets (MSFC), subject to inserting a given prescribed amount of fill. For the MDFC PIL-Fill problem, we describe three practical solution approaches based on Integer Linear Programming (ILP-I and ILP-II) and the Greedy method. For the MSFC PE-Fill problem, we describe an iterated greedy method that integrates call to an industry static timing analysis tool. We test our methods on layout testcases obtained from industry. Compared with the normal fill method [3], our ILP-11 method for MDFC PIL-Fill problem achieves between 25% and 90% reduction in terms of total weighted edge delay (roughly, a measure of sum of node slacks) impact while maintaining identical quality of the layout density control; and our iterated greedy method for MSFC PIL-Fill problem also shows significant advantage with respect to the minimum slack of nets on post-fill layout.

Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion

“…Furthermore, the impact on the fringing component of capacitance is not significant when considering small floating dummy [4]. Therefore, we focus on a model for the coupling capacitance change.…”

“…Therefore, we focus on a model for the coupling capacitance change. For the coupling capacitance, the parallel plate capacitance model can be applied [4]. Using the notation in Fig.…”

“…Finally, we can combine the intra-and inter-layer dummy models to represent the total capacitance increment model by metal fills considering 3-D effects Ctot w dummy = Ctot w odummy +Cc inc (intra)+Cg inc (inter) 2 C c inc (i) = "1T 2BS + (m 01)DS 2DW i 2n i C g inc (i) = C g (H i 0T i01 )0C g (H i ) : (4) However, in real designs not all the space under a signal layer is occupied by dummy metals, and it is likely that there are orthogonal signal interconnects in the adjacent layers. We can define as the ratio of the metal dummy area to signal space.…”

Energy-Minimization Model for Fill Synthesis

“…This is achieved by finding the potential bonds in the grid such that if the fill is placed on these bonds and the bonds are activated, the bond values between electrons of a fill are minimized. We can write this as: [3] Move electrons in to next orbit [4] if (electrons in can be placed here) [5] if´ ѯ ¾µ [6] È Ñ Ò ×Ø Ñ Ò¯ [7] else [8] È Ñ Ò ×Ø Ñ¯ [9] if ( Ñ Ò ) [10] Ñ Ò ; [11] record location with minimum force [12] until (All orbits for are tried) [13] Place electrons to the orbit with minimum force [14] Declare the locations surrounding this orbit as illegal Here, indicates Ø electron, indicates Ø energy level. Ñ Ü is the maximum number of energy levels.…”

“…[7] has proposed a window-based solution to the metal fill problem such that a density bound is preserved and variability across windows is reduced during metal fill insertion. [8] has introduced a performance-driven insertion method, either to minimize total delay impact or to maximize minimum slack.…”