Performance Evaluation of Type-3 PLLs Under Wide Variation in Input Voltage and Frequency

Aravind, C. K.; Rani, B. Indu; Chakkarapani, M.; Guerrero, Josep M.; Ilango, G. Saravana; Nagamani, C.

doi:10.1109/jestpe.2017.2679750

Cited by 17 publications

(7 citation statements)

References 29 publications

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“…The performance of the PLL in unbalanced conditions is better than the performance of conventional PLL systems. The introduction of a feed-forward path minimizes the frequency error and improves the dynamic performance in the feed-forward frequency PLL (FPLL) [20,23]. The performance under large frequency deviations still deteriorates since the consideration of a moving average filter, which improves filtering characteristics.…”

Section: Introductionmentioning

confidence: 99%

An Adaptive Feed-Forward Phase Locked Loop for Grid Synchronization of Renewable Energy Systems under Wide Frequency Deviations

Kathiresan¹,

Jeyaraj²,

Sivaprakash³

et al. 2020

Sustainability

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Synchronization is a crucial problem in the grid-connected inverter’s control and operation. A phase-locked loop (PLL) is a typical grid synchronization strategy, which ought to have a high resistance to power system uncertainties since its sensitivity influences the generated reference signal. The traditional PLL catches the phase and frequency of the input signal via the feedback loop filter (LF). In general, to enhance the steady-state capability during distorted grid conditions generally, a filter tuned for nominal frequency is used. This PLL corrects large frequency deviations around the nominal frequency, which increases the PLL’s locking time. Therefore, this paper presents an adaptive feed-forward PLL, where the input signal frequency and phase under large frequency deviations are tracked precisely, which overcomes the above-mentioned limitations. The proposed adaptive PLL consists of a feedback loop that reduces the phase error. The feed-forward loop predicts the frequency and phase error, and the frequency adaptive FIR filter reduces the ripples in output, which is due to input distortions. The adaptive mechanism adjusts the gain of the filter in accordance with the supply frequency. This reduces the phase and frequency error and also decreases the locking time under wide frequency deviations. To verify the effectiveness of the proposed adaptive feed-forward PLL, the system was tested under different grid abnormal conditions. Further, the stability analysis has been carried out via a developed prototype test platform in the laboratory. To bring the proposed simulations into real-time implementations and for control strategies, an Altera Cyclone II field-programmable gate array (FPGA) board has been used. The obtained results of the proposed PLL via simulations and hardware are compared with conventional techniques, and it indicates the superiority of the proposed method. The proposed PLL effectively able to tackle the different grid uncertainties, which can be observed from the results presented in the result section.

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Section: Introductionmentioning

confidence: 99%

An Adaptive Feed-Forward Phase Locked Loop for Grid Synchronization of Renewable Energy Systems under Wide Frequency Deviations

Kathiresan¹,

Jeyaraj²,

Sivaprakash³

et al. 2020

Sustainability

Self Cite

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“…To overcome the shortcoming of type-2 PLLs, type-3 PLLs have been developed [6,7,[12][13][14][15]. However, standard type-3 PLLs have slow dynamic performance and are not absolutely stable due to their finite gain margin (GM).…”

Section: Introductionmentioning

confidence: 99%

“…An attempt to resolve the problem of instability with threephase type-3 PLLs is presented in [6,[12][13][14][15]. The approaches employed in these works can be categorised into two broad categories: single-loop and the use of two parallel tracking paths.…”

Section: Introductionmentioning

confidence: 99%

Gain compensation approach for low‐voltage ride‐through and dynamic performance improvement of three‐phase type‐3 PLL

Bamigbade

Khadkikar

Hosani³

et al. 2020

IET Power Electronics

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Despite the ability of type-3 phase-locked loop (PLL) to provide zero steady-state error when a three-phase voltage experiences frequency ramp change, its major drawback is slow dynamic performance and instability during voltage sag condition. In this paper, by obtaining the linearised model of PLL, instability associated with the presence of voltage amplitude within the PLL control loop is illustrated. Furthermore, analysis of two common techniques employed in improving PLL stability (high phase margin design and use of phase-lead compensator) is presented and their inapplicability to three-phase type-3 PLL is revealed. Thus, to address the said problems, a gain compensation technique is proposed in this paper. In the proposed approach, the PLL loop gain is adjusted by inserting a DC gain within the PLL control loop when the frequency of supply voltage deviates from its nominal value. The inserted DC gain compensates for reduction in voltage amplitude within the PLL control loop, thus, enhancing PLL's stability especially during voltage sags. Also, the gain increases PLL's bandwidth thereby improving its estimation speed. Effectiveness of the proposed solution is confirmed through experimental studies and it is compared with five existing type-3 PLL schemes and a type-2 PLL.

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“…Several researches proposed higher-order synchronization schemes such as Type-3 PLL/Type-2 FLL to compensate for the phase angle error during the frequency ramp. However, these schemes degrade the system stability and the transient response [9][10]. The synchronous reference frame phaselocked loop (SRF-PLL) is widely used as a synchronization scheme, and can be looked at a second-order closed-loop control system [11].…”

mentioning

confidence: 99%

“…Type-1 PLL is characterized by having only one integrator in its control loop resulting in fast dynamic response and high stability margin [11]. However, both Type-1 and Type-2 PLLs cannot achieve zero average steady-state phaseerror in the presence of frequency drifts [10][11][12][13]. The phase angle steady-state error during frequency drift is tackled by introducing Type-3 PLL with three cascaded integrators resulting in degradations in both the dynamic response and the stability margin [11], [14][15][16][17].…”

mentioning

confidence: 99%

Advanced Type-1c FLL for Enhancing Converters Synchronization During Frequency Drift

Beshr

Moursi

Hamed

et al. 2021

IEEE Trans. Power Delivery

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This paper introduces a novel out-loop compensation scheme with a selective filtering stage for Type-1 Frequency Locked Loop (FLL) to obtain the same features of Type-2 FLL in response to frequency drift. The proposed scheme can eliminate the phase angle error during frequency drift without compromising its benefits of the low order control system. The performance of the proposed Type1-c FLL is evaluated with alternatively employed Delayed Signal Cancellation (DSC), Low Pass Filter (LPF) with selective harmonics filtering and multiple second-order generalized integrator (MSOGI) as a pre-filtering stage under the various grid disturbances. The effects of each filtering scheme on the dynamic response and harmonics mitigation are identified. As each filter has a distinct advantage in response to each grid disturbance, a selective control approach is used to insert the most suitable filter based on the severity of the grid disturbance to achieve the best performance. A comprehensive study is conducted to demonstrate the superior performance of the proposed schemes with both simulation and experimental validation. In addition, the potential application of the proposed Type-1c FLL for enhancing the islanded microgrid operation has been presented and verified.

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Performance Evaluation of Type-3 PLLs Under Wide Variation in Input Voltage and Frequency

Cited by 17 publications

References 29 publications

An Adaptive Feed-Forward Phase Locked Loop for Grid Synchronization of Renewable Energy Systems under Wide Frequency Deviations

An Adaptive Feed-Forward Phase Locked Loop for Grid Synchronization of Renewable Energy Systems under Wide Frequency Deviations

Gain compensation approach for low‐voltage ride‐through and dynamic performance improvement of three‐phase type‐3 PLL

Advanced Type-1c FLL for Enhancing Converters Synchronization During Frequency Drift

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