Gain compensation approach for low‐voltage ride‐through and dynamic performance improvement of three‐phase type‐3 PLL

Abstract

Despite the ability of type-3 phase-locked loop (PLL) to provide zero steady-state error when a three-phase voltage experiences frequency ramp change, its major drawback is slow dynamic performance and instability during voltage sag condition. In this paper, by obtaining the linearised model of PLL, instability associated with the presence of voltage amplitude within the PLL control loop is illustrated. Furthermore, analysis of two common techniques employed in improving PLL stability (high phase margin design and use of phase-lead compensator) is presented and their inapplicability to three-phase type-3 PLL is revealed. Thus, to address the said problems, a gain compensation technique is proposed in this paper. In the proposed approach, the PLL loop gain is adjusted by inserting a DC gain within the PLL control loop when the frequency of supply voltage deviates from its nominal value. The inserted DC gain compensates for reduction in voltage amplitude within the PLL control loop, thus, enhancing PLL's stability especially during voltage sags. Also, the gain increases PLL's bandwidth thereby improving its estimation speed. Effectiveness of the proposed solution is confirmed through experimental studies and it is compared with five existing type-3 PLL schemes and a type-2 PLL.

Improved Performance of M-Class PMUs Based on a Magnitude Compensation Model for Wide Frequency Deviations

“…It is worth mentioning that a TVE of 1% corresponds to a maximum magnitude error of 1%, whenever the error in phase angle is zero. On the other hand, sinusoidal frequency variations are common electrical conditions in power systems [33][34][35][36]. By considering that the proposal aims to compensate magnitude under wide frequency deviations, the aforementioned condition is also analyzed in this work although the Std.…”

“…(M-class filters), which have already been tested; besides, these tests are not related with frequency deviations. Although tests for sinusoidal frequency variations are not considered in the Std., a study case is also presented since those oscillations can occur in real power systems [33][34][35][36]. The obtained results show that total vector error (TVE) is less than 1% for a wide frequency deviation range.…”

An Improved Delayed Signal Cancelation for Three-Phase Grid Synchronization with DC Offset Immunity

“…The wide usage of power converters is due to their ability to convert electrical power from one form to another, making it possible to use power from different sources and to power different devices with different requirements. PLLs are also used in sensorless control of electrical machines [5], power quality indices [6,7], and islanding detection [8].…”

Performance improvement of a three‐phase PLL under distorted grid conditions based on frequency adaptive hybrid pre‐filtering

“…However, the CDSC structure causes a large delay and increases the implementation complexity. Many advanced PLLs also have been proposed by adding other filters in the loop, such as type-3 filters [24], Kalman-filters [25], notch filters (NFs) [26][27][28], and complex-coefficient filters (CCFs) [29,30]. However, adding NFs or CCFs in the PLL involves a tradeoff between filtering capability and computational burden, which is challenging for practical applications.…”