Performance evaluation of the sparse matrix-vector multiplication on modern architectures

Abstract

In this paper, we revisit the performance issues of the widely used sparse matrix-vector multiplication (SpMxV) kernel on modern microarchitectures. Previous scientific work reports a number of different factors that may significantly reduce performance. However, the interaction of these factors with the underlying architectural characteristics is not clearly understood, a fact that may lead to misguided, and thus unsuccessful attempts for optimization. In order to gain an insight into the details of SpMxV performance, we conduct a suite of experiments on a rich set of matrices for three different commodity hardware platforms. In addition, we investigate the parallel version of the kernel and report on the corresponding performance results and their relation to each architecture's specific multithreaded configuration. Based on our experiments, we extract useful conclusions that can serve as guidelines for the optimization process of both single and multithreaded versions of the kernel.

Parallelization of a Mathematical Model to Evaluate a Cca Application for Vanets

“…This operation is considered as a relevant computational kernel in scientific applications, which performs not optimally on modern processors because of the lack of compromise between memory and computing power and irregular memory access patterns ). In general, we find quite a lot of done work in the field of sparse matrix-vector multiplications using parallelization techniques (Kotakemori et al, 2008;Goumas et al, 2009;Williams et al, 2009). These papers study in depth the optimal performance of this operation, but in this paper, we show that even using a simpler parallelization routine, the computation time is noticeably shortened.…”

Speeding Up the Evaluation of a Mathematical Model for VANETs Using OpenMP

“…This operation is considered as a relevant computational kernel in scientific applications, which performs not optimally on modern processors because of the lack of compromise between memory and computing power and irregular memory access patterns [5]. In general, we find quite a lot of done work in the field of sparse matrix-vector multiplications using parallelization techniques [6], [7], [8]. These papers study in depth the optimal performance of this operation, but in this paper, we show that even using a simpler parallelization routine, the computation time is noticeably shortened.…”

Adapt or become extinct!

“…Past work [12,2] has identified the memory subsystem as the main performance bottleneck of the SpMV kernel. Obviously, this problem becomes more severe in a multithreaded environment, where multiple cores access the main memory.…”