Performance evaluation of hetero-stacked TFET for variation in lateral straggle and its application as digital inverter

Vanlalawmpuia, K.; Saha, Rajesh; Bhowmick, Brinda

doi:10.1007/s00339-018-2121-4

Cited by 14 publications

(6 citation statements)

References 29 publications

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“…As the lateral straggle is increased, the RF/analog performance improves but degrades the linearity behavior of GM‐TFET 16 . Similarly, the RF/analog and linearity characteristic of hetero‐stacked source TFET is highlighted due to variation in lateral straggle 29 . The analytical modeling of DC and RF/analog parameters is developed for a vertical surrounding gate (VSG) TFET and a good agreement is obtained with the simulated data 30 .…”

Section: Introductionmentioning

confidence: 77%

Influence of dielectric material near tunnel junction on analog/ RF and linearity figure of merits in hetero dielectric ( HG ) TFET : A detailed study

Saha

Sahu

2021

Int J RF Microw Comput Aided Eng

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In this work, the effect of dielectric material near the source region on analog/RF and linearity figure of merits in hetero gate TFET (HG‐TFET) are investigated through Technology Computer Aided Design device simulator. The various dielectric materials considered in this study are SiO2, Al2O3, and HfO2. The several RF/analog metrics studied in this work are transconductance (gm), output conductance (gd), gain (gm/gd), gate capacitance, cut‐off frequency, and gain frequency product. Furthermore, the various linearity parameters discussed are higher order derivative of gm (gm2 and gm3), voltage intercept points (VIP2 and VIP3), 3rd‐order input intercept power, and 3rd‐order intermodulation power for different high‐k dielectric near the source region in HG‐TFET. Results reveal that RF/analog performance is improved, whereas, the linearity characteristic is suppressed in HG‐TFET using HfO2 as the gate dielectric near the source.

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Section: Introductionmentioning

confidence: 77%

Influence of dielectric material near tunnel junction on analog/ RF and linearity figure of merits in hetero dielectric ( HG ) TFET : A detailed study

Saha

Sahu

2021

Int J RF Microw Comput Aided Eng

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“…It is also reported that RF/analog and linearity behavior of DG TFET is suppressed with rise in σ value 27,28 . Over course of time, analysis on effect of σ on RF/analog characteristic are presented in gate modulated 29 and hetero‐stacked TFETs 30 . Recently, the effect of source/drain gradient for the variation in lateral straggle parameter in terms of DC and RF performance is highlighted in Ge epitaxial DG TFET 31 .…”

Section: Introductionmentioning

confidence: 98%

“…27,28 Over course of time, analysis on effect of σ on RF/analog characteristic are presented in gate modulated 29 and hetero-stacked TFETs. 30 Recently, the effect of source/drain gradient for the variation in lateral straggle parameter in terms of DC and RF performance is highlighted in Ge epitaxial DG TFET. 31 Most recently, it is shown that the linearity characteristics in Ge-source DMDG-TFET degrade as the value of σ increases.…”

Section: Introductionmentioning

confidence: 99%

Analysis on effect of lateral straggle on analog, high frequency and DC parameters in Ge‐source DMDG TFET

Saha

Panda

Goswami

et al. 2021

Int J RF Mic Comp-Aid Eng

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The diffusion of doping concentration in source/drain regions through ion implantation technique extents to the channel, which decreases the inversion portion of channel and results in variation of device behavior. In this paper, by merging the advantages of Ge‐source TFET and dual material gate (DMG) TFET, a new device named as Ge‐source dual material double gate (DMDG) TFET is proposed. We have investigated DC parameters like drain current vs gate bias, drain current vs drain bias, subthreshold swing (SS), and current ratio (ION/IOFF) by changing the lateral straggle parameter (σ) from 0 to 5 nm through TCAD device simulator in proposed TFET. The RF/analog behavior like transconductance (gm), output conductance (gd), intrinsic gain (gm/gd), total gate capacitance (Cgg), cut‐off frequency (fc), transconductance generation factor (TGF), transconductance frequency product (TFP), gain frequency product (GFP), and gain transconductance frequency product (GTFP) are reported for different σ values in proposed TFET. It is found that both DC and RF/analog figure of merits are a function of σ. It is perceived that ION as well as RF/analog characteristics are improved, whereas, short channel parameter degrades with increase in σ. Finally, the effect of σ on noise performance and s‐parameters are highlighted in proposed device.

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“…Thus, the leakage current of a TFET is very low and also it is able to theoretically achieve a smaller SS [16][17][18]. Besides all of these merits, the Si-based conventional TFETs have two major drawbacks [19][20][21][22]: low on-state current (I on ) due to the limited BTBT probability and ambipolar conduction (I amb ) which is caused by BTBT at drain junction. In order to overcome these drawbacks, various techniques have been reported in earlier research works i.e.…”

Section: Introductionmentioning

confidence: 99%

Representation of an engineered double-step structure SOI-TFET with linear doped channel for electrical performance improvement: a 2D numerical simulation study

Meshkin¹,

Ziabari²,

Jordehi³

2020

Semicond. Sci. Technol.

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In this paper, a novel double-step (DS) structure tunnel field-effect transistor with a linear doping profile channel (DSS-LDC-TFET) is presented. The use of a step-shaped structure near the source/channel interface leads to the large tunneling junction area because the band-to-band tunneling of the carriers occurs perpendicularly along the conducting path in the channel. The step-shape of the channel/drain interface reduces the electric field distribution near the drain junction which helps to suppress the ambipolar behavior. Further, the DS structure of the body suppresses the ambipolar conduction due to increasing the effective length of channel area along the device. Therefore, the height of the steps in the proposed structure plays an important role in the device characteristics. The doping profile in the channel region is considered to be linear. The maximum value of the doping concentration is at the source side and linearly decreases to its minimum value along the x-axis. Numerical simulation results show that using the linear doping distribution at the channel improves device behavior through reducing the tunneling barrier width at the source/channel interface. The optimum length for the linear-doped part of the channel is selected to maximize the on-state current without degrading much the off-state current. Finally, the comparative study between DSS-LDC-TFET with the conventional silicon-on-insulator tunnel field-effect transistor is presented.

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Performance evaluation of hetero-stacked TFET for variation in lateral straggle and its application as digital inverter

Cited by 14 publications

References 29 publications

Influence of dielectric material near tunnel junction on analog/ RF and linearity figure of merits in hetero dielectric ( HG ) TFET : A detailed study

Influence of dielectric material near tunnel junction on analog/ RF and linearity figure of merits in hetero dielectric ( HG ) TFET : A detailed study

Analysis on effect of lateral straggle on analog, high frequency and DC parameters in Ge‐source DMDG TFET

Representation of an engineered double-step structure SOI-TFET with linear doped channel for electrical performance improvement: a 2D numerical simulation study

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