Performance Evaluation of a Vector Supercomputer SX-Aurora TSUBASA

Komatsu, Kazuhiko; Momose, Shintaro; Isobe, Yoko; Watanabe, Osamu; Musa, Akihiro; Yokokawa, Mitsuo; Aoyama, Toshikazu; Sato, Masayuki; Kobayashi, Hiroaki

doi:10.1109/sc.2018.00057

Cited by 83 publications

(43 citation statements)

References 15 publications

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“…The NEC SX-Aurora TSUBASA vector architecture [15,20] consists of multiple vector engines (VE), installed into a vector host (VH), which is a typical x86 node. Vector engines are used as a primary processors for executing vectorised applications, while vector host is used as a secondary processor for executing basic operating system (OS) functions, as well as some scalar computations offloaded from the VE.…”

Section: Nec Sx-aurora Tsubasamentioning

confidence: 99%

Developing an Architecture-independent Graph Framework for Modern Vector Processors and NVIDIA GPUs

2020

JSFI

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This paper describes the first-in-the-world attempt to develop an architectural-independent graph framework named VGL, designed for different modern architectures with high-bandwidth memory. Currently VGL supports two classes of architectures: NEC SX-Aurora TSUBASA vector processors and NVIDIA GPUs. However, VGL can be easily extended to other architectures due to its flexible software structure. VGL is designed to provide users with the possibility of selecting the most suitable architecture for solving a specific graph problem on a given input data, which, in return, allows to significantly outperform existing frameworks and libraries, developed for modern multicore CPUs and NVIDIA GPUs. Since VGL uses an identical set of computational and data abstractions for all architectures, its users can easily port graph algorithms between different target architectures without any source code modifications. Additionally, in this paper we show how graph algorithms should be implemented and optimised for NVIDIA GPU and NEC SX-Aurora TSUBASA architectures, demonstrating that both architectures have multiple similar properties and hardware features.

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Section: Nec Sx-aurora Tsubasamentioning

confidence: 99%

Developing an Architecture-independent Graph Framework for Modern Vector Processors and NVIDIA GPUs

2020

JSFI

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“…The SX-Aurora does not run an operating system. It supports multiple modes of operation described in [7]. Most attractive to us is the VE execution mode: all application code is run on the accelerator, while system calls are directed to and executed on the host CPU.…”

Section: Programming Models and Software Stackmentioning

confidence: 99%

Lattice QCD on a novel vector architecture

Huth¹,

Meyer²,

Wettig³

2020

Proceedings of 37th International Symposium on Lattice Field Theory — PoS(LATTICE2019)

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The SX-Aurora TSUBASA PCIe accelerator card is the newest model of NEC's SX architecture family. Its multi-core vector processor features a vector length of 16 kbits and interfaces with up to 48 GB of HBM2 memory in the current models, available since 2018. The compute performance is up to 2.45 TFlop/s peak in double precision, and the memory throughput is up to 1.2 TB/s peak. New models with improved performance characteristics are announced for the near future. In this contribution we discuss key aspects of the SX-Aurora and describe how we enabled the architecture in the Grid Lattice QCD framework.

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“…1 lists specifications of SX-ACE and SX-Aurora TSUBASA and options of each Fortran compiler. [8,17]. It consists of one or more card-type vector engines (VEs) and a vector host (VH).…”

Section: Sx-acementioning

confidence: 99%

Effects of Using a Memory Stalled Core for Handling MPI Communication Overlapping in the SOR Solver on SX-ACE and SX-Aurora TSUBASA

Soga

Yamaguchi

Mathur³

et al. 2020

JSFI

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Modern high-performance computing (HPC) systems consist of a large number of nodes featuring multi-core processors. Many computational fluid dynamics (CFD) codes utilize a Message Passing Interface (MPI) to exploit the potential of such systems. In general, the MPI communication costs increase as the number of MPI processes increases. In this paper, we discuss performance of the code in which a core is used as a dedicated communication core when the core cannot contribute to the performance improvement due to memory-bandwidth limitations. By using the dedicated communication core, the communication operations are overlapped with computation operations, thus enabling highly efficient computation by exploiting the limited memory bandwidth and idle cores. The performance evaluation shows that this code can hide the MPI communication times of 90% on the supercomputer SX-ACE system and 80% on the supercomputer SX-Aurora TSUBASA system, and the performance of the successive over-relaxation (SOR) method is improved by 32% on SX-ACE and 20% on SX-Aurora TSUBASA.

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Performance Evaluation of a Vector Supercomputer SX-Aurora TSUBASA

Cited by 83 publications

References 15 publications

Developing an Architecture-independent Graph Framework for Modern Vector Processors and NVIDIA GPUs

Developing an Architecture-independent Graph Framework for Modern Vector Processors and NVIDIA GPUs

Lattice QCD on a novel vector architecture

Effects of Using a Memory Stalled Core for Handling MPI Communication Overlapping in the SOR Solver on SX-ACE and SX-Aurora TSUBASA

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