Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores

Abstract

Device level heterogeneity promises high energy efficiency over a larger range of voltages than a single device technology alone can provide. In this paper, starting from device models, we first present ground-up modeling of CMOS and TFET cores, and verify this model against existing processors. Using our core models, we construct a 32-core TFET-CMOS heterogeneous multicore. We then show that it is a very challenging task to identify the ideal runtime configuration to use in such a heterogeneous multicore, which includes finding the best number/type of cores to activate and the corresponding voltages/frequencies to select for these cores. In order to effectively utilize this heterogeneous processor, we propose a novel automated runtime scheme. Our scheme is designed to automatically improve the performance of applications running on heterogeneous CMOS-TFET multicores operating under a fixed power budget, without requiring any effort from the application programmer or the user. Our scheme combines heterogeneous thread-to-core mapping, dynamic work partitioning, and dynamic power partitioning to identify energy efficient operating points. With simulations we show that our runtime scheme can enable a CMOS-TFET multicore to serve a diversity of workloads with high energy efficiency and achieve 21% average speedup over the best performing equivalent homogeneous multicore.

Energy and Peak Power Efficiency Analysis for the Single Voltage Approximation (SVA) Scheme

“…Proof: For Equation (16) to be continuous, we match both parts and find the w M for which the equality holds. That is,…”

“…In this aspect, there are many works in the literature that focus on improving performance under a given power budget [16], [18], [21]. However, these works do not address the issue of energy consumption and do not provide any timing guaranties, making them unsuited for real-time systems.…”

“…E * ↓ from Equation(16), and by using Newton's Method for Equation(12), with γ = 3, α = 0.27 W GHz 3 , β = 0.52 W GHz , κ = 0.5 W, M = 16, L = 1 sec., constant M i=1 w i = 5 · 10 9 cycles second , and w 1…”

Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures

“…Compared to the previously reported TFET designs optimized for dynamic operation power (LOP HTFET [10], the low leakage HTFET employs a relaxed channel length (10% relaxation) to achieve reduced static leakage power, since a reduced short channel effect has been observed in 20nm gate TFETs [11]. This design of LSTP HTFET still offers a desired drive-current at low supply voltage with an optimized leakage power, since the field across the tunnel junction is the primary determinant of the performance.…”

“…In prior works such as [10], the processor critical path delay have been modeled using multipipeline stage ring oscillators. However, due to the diversity in critical paths in more complex out-of-order cores, and the corresponding impact of non-logic components such as interconnects, a this model may not be sufficiently accurate to model the performance and power characteristics of these cores.…”