Performance enhancement of NUMA multiprocessor systems with on-demand memory migration

Mishra, Vipul Kumar; Mehta, D.A.

doi:10.1109/iadcc.2013.6506812

Cited by 4 publications

(3 citation statements)

References 7 publications

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“…Task placement affects contention between resources for the cache and cores, and data placement affects the memory access cost for a task. To utilize system resources more efficiently and increase performance, many studies [7][8][9][10][11][12][13][14][15] design specific placements of tasks and data to decrease resource contention, balance the loads in the cores, and reduce access to remote memory. The solutions focus on improving the performance of Symmetric Multi-processing (SMP) and Non-Uniform Memory Access (NUMA) [2] systems.…”

Section: Technological Background and Related Workmentioning

confidence: 99%

“…Migrating memory pages to the NUMA node on which their requesting task is currently running reduces remote memory access. Mishra and Mehta [15] proposed an on-demand memory migration policy that migrates only the referenced pages to the current node where the requesting task is running. Terboven et al [11] proposed a user-level implementation of a Next-touch approach in Linux.…”

Section: Related Workmentioning

confidence: 99%

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Thread-Aware Mechanism to Enhance Inter-Node Load Balancing for Multithreaded Applications on NUMA Systems

Chiang

2021

Applied Sciences

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NUMA multi-core systems divide system resources into several nodes. When an imbalance in the load between cores occurs, the kernel scheduler’s load balancing mechanism then migrates threads between cores or across NUMA nodes. Remote memory access is required for a thread to access memory on the previous node, which degrades performance. Threads to be migrated must be selected effectively and efficiently since the related operations run in the critical path of the kernel scheduler. This study focuses on improving inter-node load balancing for multithreaded applications. We propose a thread-aware selection policy that considers the distribution of threads on nodes for each thread group while migrating one thread for inter-node load balancing. The thread is selected for which its thread group has the least exclusive thread distribution, and thread members are distributed more evenly on nodes. This has less influence on data mapping and thread mapping for the thread group. We further devise several enhancements to eliminate superfluous evaluations for multithreaded processes, so the selection procedure is more efficient. The experimental results for the commonly used PARSEC 3.0 benchmark suite show that the modified Linux kernel with the proposed selection policy increases performance by 10.7% compared with the unmodified Linux kernel.

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Section: Technological Background and Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Thread-Aware Mechanism to Enhance Inter-Node Load Balancing for Multithreaded Applications on NUMA Systems

Chiang

2021

Applied Sciences

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“…Their experiments showed that the kernel‐based implementation is 30% faster than the user‐space model and has much lower overhead when migrating small memory. Mishra and Mehta also presented a memory migration on‐demand policy similar to the Next‐touch approach. Their implementation is also performed using the madvise() system call invoked by applications and a modified kernel page fault handler.…”

Section: Technology Background and Related Workmentioning

confidence: 99%

Memory‐aware kernel mechanism and policies for improving internode load balancing on NUMA systems

Chiang

et al. 2019

Softw Pract Exp

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Although nonuniform memory access architecture provides better scalability for multicore systems, cores accessing memory on remote nodes take longer than those accessing on local nodes. Remote memory access accompanied by contention for internode interconnection degrades performance. Properly mapping threads to cores and data accessed to their nodes can substantially improve performance and energy efficiency. However, an operating system kernel's load-balancing activity may migrate threads across nodes, which thus messes up the thread mapping. Besides, subsequent data mapping behavior pays for the cost of page migration to reduce remote memory access. Once unsuitable threads are migrated, it is detrimental to system performance. This paper focuses on improving the kernel's internode load balancing on nonuniform memory access systems. We develop a memory-aware kernel mechanism and policies to reduce remote memory access incurred by internode thread migration. The Linux kernel's load balancing mechanism is modified to incorporate selection policies in the internode thread migration, and the kernel is modified to track the amount of memory used by each thread on each node. With this information, well-designed policies can then choose suitable threads for internode migration. The purpose is to avoid migrating a thread that might incur relatively more remote memory access and page migration. The experimental results show that with our mechanism and the proposed selection policies, the system performance is substantially increased when compared with the unmodified Linux kernel that does not consider memory usage and always migrates the first-fit thread in the runqueue that can be migrated to the target central processing unit.

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Enhancing Inter-Node Process Migration for Load Balancing on Linux-Based NUMA Multicore Systems

Chiang

et al. 2018

2018 IEEE 42nd Annual Computer Software and Applications Conference (COMPSAC)

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Performance enhancement of NUMA multiprocessor systems with on-demand memory migration

Cited by 4 publications

References 7 publications

Thread-Aware Mechanism to Enhance Inter-Node Load Balancing for Multithreaded Applications on NUMA Systems

Thread-Aware Mechanism to Enhance Inter-Node Load Balancing for Multithreaded Applications on NUMA Systems

Memory‐aware kernel mechanism and policies for improving internode load balancing on NUMA systems

Enhancing Inter-Node Process Migration for Load Balancing on Linux-Based NUMA Multicore Systems

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