Performance enhancement of FINFET and CNTFET at different node technologies

Hajare, Raju; Lakshminarayana, C.; Raghunandan, G. H.; Raj, Cyril Prasanna

doi:10.1007/s00542-015-2468-9

Cited by 25 publications

(11 citation statements)

References 7 publications

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“…In this FinFET device source and drain regions are connected via thin fins used as a channel and the gate wraps three sides of the fin for better control of the flow of charge carriers which further reduces the leakage current [9,10]. However, FinFET due to its vertical and rectangular geometry holds issues such as corner effects, parasitic capacitance, gate electrostatics and process complexity etc [11].…”

Section: Introductionmentioning

confidence: 99%

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

Singh

Prasad

Kumar

2020

Mater. Res. Express

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The device dimensions have been consistently scaling down since many developing technologies need smaller and faster integrated circuits for advancement and improvement in both performance and device density. Device dimensions have been decreased drastically from micron to sub nanometer regime. Traditionally, miniaturizing and performance improvement was obtained by tweaking the MOSFET-reducing the channel lengths and gate oxide thickness, increasing dielectric constants etc Unfortunately at 22 nm node it reached a dead end. However, at 22 nm node the tri-gate FinFET introduced by Intel Corporation have provided many possibilities for scaling the dimensions with satisfactory device performance. Further, the gate all around (GAA) carbon nano tube field effect transistor (CNTFET) provides high gain, high trans-conductance, reduced short channel effects and conditions for scaling the technology to sub nano scale. Due to surround gate structure this GAA CNTFET offers better control with integration of high_k stacked dielectric wrapped around the channel. In this paper, first properties of Carbon nanotube (CNT) have been comprehensively studied for various chirality and diameter and parameters viz. Density of States (DoS) and Band gap (E g ) are extracted by using MedeA tool's VASP 5.3 module. The various CNT chirality have been optimized and the extracted parameters used to model and simulate CNTFET using Silvaco's Devedit3D, Atlas and Atlas3D modeling and simulation modules. The device input (I D -V GS ) and output (I D -V DS ) characteristics have been intensively studied and parameters including I ON /I OFF ratio, DIBL, sub threshold slope extracted and compared with the conventional devices. The GAA CNTFET device at 0.8 V supply voltage exhibits threshold voltage (V TH ) 0.254 V, drain induced barrier lowering (DIBL) 72 mV/V, sub-threshold swing (SS) 63.29 mV/dec, and I ON/ I OFF ratio 7.17e+06. The results demonstrate improvement in device parameters for the GAA CNTFET device as compared to bulk silicon and FinFET devices.

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Section: Introductionmentioning

confidence: 99%

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

Singh

Prasad

Kumar

2020

Mater. Res. Express

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“…This degrades the robustness of dynamic circuits. 8 Specifically, with CNTs, we can acquire better performance at high frequencies. The leakage current, for high Fan-in domino logic rises due to large number of parallel paths in the evaluation block.…”

Section: Introductionmentioning

confidence: 99%

“…7 The current driving capacity of CNT is much better than CMOS as they have better electrical properties than silicon. 8 Specifically, with CNTs, we can acquire better performance at high frequencies.…”

Section: Introductionmentioning

confidence: 99%

A 1‐bit full adder using CNFET based dual chirality high speed domino logic

Garg

Gupta

Pandey³

2019

Circuit Theory & Apps

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CNFET devices are preferred over CMOS devices for designing high-speed digital circuits. This paper introduces a new technique Dual Chirality High-speed Domino Logic (DCHSDL) for implementing low power and high-speed domino circuits in CNFET technology. Simulations are carried out for 32 nm Stanford CNFET model in HSPICE for 2, 4, 8 and 16 input domino OR gates at a clock frequency of 200 MHz on a DC supply voltage of 0.9 V. The proposed domino technique shows maximum power reduction of 82.55% and maximum delay reduction of 57.97% compared to CPVT technique in CNFET technology at a frequency of 200 MHz. The proposed circuit shows maximum power reduction of 97.90% compared to its analogous circuit in CMOS technology for a 2-input domino OR gate. The proposed technique shows maximum improvement of 1.05× to 1.63× in unity noise gain (UNG) compared to various existing techniques in CNFET technology at a frequency of 200 MHz. The 1-bit Full Adderdesigned using the proposed technique shows a power reduction of 16.91% and a delay reduction of 23.64% compared to standard FDL 1-bit Full Adder. K E Y W O R D SCNFET, Domino, Dynamic, FOM, VLSI

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“…To avoid these effects as well as to improve the switching speed ad to reduce the power requirements, MOSFET's were replaced by FINFET's in design circuitry [4,5].FINFET's are multiple gate devices. These multiple gates provide better control over the channel and hence reduce the short channel effects [6]. FINFET based adder in general shows an average of 94% drop in delay, 97% decrease in power dissipation over the conventional MOSFET's [7], [8].…”

Section: Introductionmentioning

confidence: 99%

Design and software characterization of finFET based full adders

Hajare

Lakshminarayana

2019

IJRES

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Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSFET’s suffers from Short Channel Effects (SCE’s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and 16T 1-bit full adders at various technology nodes using HSPICE software. Results show that FinFET based full adder design gives better performance in terms of speed, power and reliability compared to MOSFET based full adder designs. Hence FinFET are promising candidates and better replacement for MOSFET.

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Performance enhancement of FINFET and CNTFET at different node technologies

Cited by 25 publications

References 7 publications

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

A 1‐bit full adder using CNFET based dual chirality high speed domino logic

Design and software characterization of finFET based full adders

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