Performance enhancement of field effect transistor without doping junctions using In0.3Ga0.7As/GaAs for analog/RF applications

Fallahnejad, Mohammad; Vadizadeh, Mahdi; Salehi, Alireza

doi:10.1142/s0217979219500504

Cited by 8 publications

(2 citation statements)

References 32 publications

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“…been used. 21,22 Cg is the total gate-capacitance which is a combination of quantum and oxide capacitances in series. This parameter is computed by the following formula:…”

Section: Proposed Structure and Simulation Methodsmentioning

confidence: 99%

Theoretical Analysis of Tunneling GNRFET under Local Compressive Uniaxial Strain

Abbaszadeh

Yousefi

Aderang

2020

ECS J. Solid State Sci. Technol.

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By applying %3 compressive local uniaxial strain on 2.5 nm of source and 2.5 nm of channel regions of tunneling graphene nanoribbon field-effect transistor (T-GNRFET), we propose a new local-strained source and channel (LSSC) T-GNRFET. Quantum simulations of the proposed structure have been done in mode-space non-equilibrium Green's function (NEGF) approach in ballistic regime. Simulation results show that in comparison with the conventional T-GNRFET of the same dimensions, the ONcurrent of the proposed structure has been improved considerably. Besides, the proposed structure enjoys better analog characteristics such as transconductance (g m ) and unity-gain frequency (f t ).

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“…been used. 21,22 Cg is the total gate-capacitance which is a combination of quantum and oxide capacitances in series. This parameter is computed by the following formula:…”

Section: Proposed Structure and Simulation Methodsmentioning

confidence: 99%

Theoretical Analysis of Tunneling GNRFET under Local Compressive Uniaxial Strain

Abbaszadeh

Yousefi

Aderang

2020

ECS J. Solid State Sci. Technol.

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show abstract

“…Various physics models that includes Drift-diffusion, Hydrodynamic model 22,23 Fermi-Dirac statistics, MLDA model (quantum confinement effects), 21 SRH recombination, 24 Band-toband model, 25,26 auger model, Philips unified and Lombardi mobility models, 27 slotboom bandgap narrowing model are included in simulation setup for analysis purpose.…”

Section: T E O T T 1 High K Sio High Kmentioning

confidence: 99%

Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

Ramakrishna,

Valasa,

Bhukya

et al. 2023

ECS J. Solid State Sci. Technol.

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FinFET is considered a potential contender in the era of Multigate field-effect transistors (FETs). Here, we present structural variations for Junctionless FinFET devices at the IRDS sub-5nm technology node. Four JL-FinFET novel structures are proposed, JL-MG-U-FinFET, JL-U-FinFET, JL-Inv-U-FinFET, and JL-DG-Inv-U-FinFET. The electrical and analog/RF performance of these structures are compared and it is found that JL-DG-Inv-U-FinFET gives better performance in terms of minimizing short channel effects as well as in terms of analog/radio frequency characteristics. The ION/IOFF ratio values for (JL-MG-U-FinFET, JL-U-FinFET, JL-Inv-U-FinFET, and JL-DG-Inv-U-FinFET) are observed as 8.5×106, 1.2×109, 2.04×108, and 1.1×1010, respectively. Similarly, the SS values are noted as 93.44, 70.87, 70.61, and 62.1 mV/dec for the respective configurations. The effect of variation in geometrical parameters such as gate length, U-shaped fin width, and U-shaped fin height on DC and analog/RF characteristics is also explored. It has been observed that the DC parameters such as Ion/Ioff ratio, SS are better for higher Lg, lower WU-fin, and higher HU-fin. Moreover, the JL-DG-Inv-U-FinFET-based common source amplifier produced a gain of 5.2. The results reported will aid device engineers in selecting better geometrical parameters to achieve improved JL-DG-Inv-U-FinFET performance.

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High-speed SOI junctionless transistor based on hybrid heterostructure of Si/Si0.5Ge0.5 and asymmetric spacers with outstanding analog/RF parameters

et al. 2021

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Performance enhancement of field effect transistor without doping junctions using In0.3Ga0.7As/GaAs for analog/RF applications

Cited by 8 publications

References 32 publications

Theoretical Analysis of Tunneling GNRFET under Local Compressive Uniaxial Strain

Theoretical Analysis of Tunneling GNRFET under Local Compressive Uniaxial Strain

Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

High-speed SOI junctionless transistor based on hybrid heterostructure of Si/Si0.5Ge0.5 and asymmetric spacers with outstanding analog/RF parameters

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