Performance enhancement of CMOS VLSI circuits by transistor reordering

Power conscious CAD tools and methodologies: a perspective

“…In the high volume microprocessor market segment, integration was driven by the need to increase the performance. Higher performance was achieved through the use of new architectures (e.g., super scalar and super pipelined); integrating more and more system functions on chip, increasing the processor speed and increasing the processor's ability to perform computation on larger word sizes e.g., 8, 16, and 32 b. The trend in the large, and cost…”

“…If we ignore the power dissipation due to charging and discharging of internal capacitances, it becomes obvious that high switching activity inputs should be matched with pins that have low input capacitance [16]. However, the internal power dissipation also varies as a function of the switching activities and the pin assignment of the input signals.…”

The future of custom cell generation in physical synthesis

“…The researchers in [17] automated transistor reordering and demonstrated the benefits of ordering on speed critical paths. They showed that the optimum order requires the consideration of the complete electrical environment of the circuit, specifically the input rise/fall transition rates.…”

Modeling and layout optimization of VLSI devices and interconnects in deep submicron design

“…When applied to the entire circuit, it needs to be combined with circuit timing analysis so that when a gate is optimized, the signal arrival times at its inputs are known. The reader may refer to [3] and [28] for more details. Transistor ordering has no (or little) area penalty, but the reduction on delay is limited (usually around 5%).…”